Arithmetic Processing Device Parallel Comparison Update Architecture
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Solution Overview
Problem
The processing time for comparing and updating magnitudes of information sets in arithmetic operation processing devices, particularly in subject estimating processes using deep learning, is excessively long due to the need for extensive comparisons and updates of class reliability information, which is exacerbated in moving image applications.
Innovation Solution
The implementation of a parallel processing architecture with multiple stages of comparison update parts, a data storage buffer, and a memory control part that optimizes the comparison and update process by storing and managing information sets and zero information buffers to reduce unnecessary comparisons and maintain processing order, allowing for efficient parallel processing without altering the order of operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If sequential comparison and update process is used for information sets, then processing accuracy is maintained, but processing time becomes excessively long
Solution Approach 1:
The processing system is divided into multiple stages (first stage, second stage, third stage) with multiple comparison update parts in each stage. This segmentation allows parallel processing of information sets across different stages while maintaining the sequential comparison logic within each stage, thereby reducing overall processing time without sacrificing accuracy.
Solution Approach 2:
The patent introduces a multi-dimensional processing architecture where information sets are processed across multiple stages and parallel comparison update parts. This dimensional expansion from single-sequential processing to multi-stage parallel processing enables time reduction while preserving the accuracy of comparison operations.
2Productivity
If multiple comparison update parts operate in parallel, then processing speed increases, but device complexity increases
Solution Approach 1:
The parallel processing architecture is segmented into multiple discrete comparison update parts (first comparison update part, second comparison update part, etc.) organized in stages. This segmentation makes the complexity manageable by breaking down the parallel processing system into modular, reusable units that can be systematically controlled.
Solution Approach 2:
The memory control part performs preliminary actions by controlling the storage buffer to supply appropriate input data to each comparison update part in advance. This preliminary data preparation and coordination simplifies the overall system control while enabling efficient parallel operation of multiple comparison update parts.
3Measurement precision
If extensive comparisons and updates of class reliability information are performed, then subject recognition accuracy is improved, but power consumption increases
Solution Approach 1:
The patent extracts and processes only the necessary class reliability information through selective comparison and update operations. By using multiple comparison update parts that focus on specific information sets in parallel, the system performs fewer total operations compared to exhaustive sequential processing, thereby reducing power consumption while maintaining recognition accuracy.
Solution Approach 2:
The system performs partial comparison and update actions through the multi-stage parallel architecture, processing information sets in distributed stages rather than performing exhaustive sequential comparisons. This partial action approach reduces the total computational load and power consumption while achieving the necessary recognition accuracy through the coordinated operation of multiple comparison update parts.
Data Source
AI summary
An arithmetic operation processing device configured to: store first data as a comparison target value, compare the comparison target value with a comparison value having data other than the first data, update the values based on the comparison, sequentially acquire the comparison values and acquire the comparison target values of the comparison update parts, read data that initially becomes the K comparison target values, transmit the K comparison target values to the K comparison update parts of the data comparing part, when all the comparison target values are read from the data storage buffer, read all data other than the data that becomes the comparison target values from the data storage buffer, and in a case in which comparison of a second time or a subsequent time is performed, reflect update details until comparison of the previous time in the data and output resultant data to the comparison update part.