Arithmetic Processing Unit Memory Controller Throughput Optimization
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Solution Overview
Problem
In packet communication systems, variable-length access requests to memory resources lead to inefficient processing due to resource limitations, causing throughput deterioration as requests are often delayed or kept waiting.
Innovation Solution
An arithmetic processing unit with a memory controller that includes multiple buffers for different access request lengths and an arbitrator to select requests based on remaining memory resources, ensuring efficient allocation and prioritization of access requests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple variable-length access requests are processed using a single buffer, then device complexity is reduced, but throughput deteriorates due to resource contention and waiting
Solution Approach 1:
The single buffer is segmented into multiple buffers according to access request length (short, medium, long packets). Each buffer independently manages requests of its specific length range, eliminating resource contention between different packet types and improving throughput without requiring complex dynamic allocation mechanisms.
Solution Approach 2:
The patent introduces a new dimension of classification by packet length to organize access requests. Instead of using a single undifferentiated buffer, requests are distributed across multiple buffers based on their length characteristics, adding structural dimensionality that resolves resource conflicts.
2Productivity
If access requests are processed in FIFO order without prioritization, then ease of operation is maintained, but throughput deteriorates when resources are limited
Solution Approach 1:
Different arbitration strategies are applied to different buffer types based on their characteristics. Short packet buffers use priority arbitration to quickly clear small requests, while long packet buffers use FIFO ordering. This localized quality approach optimizes throughput for each packet type without requiring complex global arbitration logic.
Solution Approach 2:
The arbitration mechanism dynamically selects which buffer to service based on current resource availability and buffer states. The arbitrator adapts its behavior according to real-time conditions, such as switching between serving short packets with priority when resources are available and using FIFO when resources are constrained.
3Productivity
If the number of buffers is increased to handle different packet lengths, then throughput is improved, but device complexity increases
Solution Approach 1:
The buffer memory is segmented into distinct regions (short, medium, long packet buffers) with clear boundaries. Each segment is dedicated to specific packet length ranges, which simplifies management compared to a single large buffer requiring complex dynamic allocation and deallocation operations.
Solution Approach 2:
Instead of creating a buffer for every possible packet length variation, the patent uses a moderate number of buffers (short, medium, long) that cover the practical range of packet lengths. This partial action approach provides sufficient throughput improvement without the excessive complexity of fine-grained buffer segmentation.
Data Source
AI summary
An arithmetic processing unit including a memory controller configured to make variable-length access requests allowing a plurality of lengths to a memory, the memory controller comprising: a plurality of buffers configured to hold the access requests for each of the lengths of the access requests; and an arbitrator configured to select one of access requests stored in the plurality of buffers in accordance with a number of remaining resources of the memory.