Arithmetic Processing Device Instruction Retry Mechanism
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Solution Overview
Problem
In semiconductor devices, instructions determined to be non-retryable due to error detection cycles are not accurately distinguished from retryable ones, leading to deteriorated processing performance and reliability, as the architecture fails to consider the order of commits in out-of-order execution.
Innovation Solution
The semiconductor device implements a system where each instruction is assigned a count value indicating the number of cycles since completion, allowing the identification of retryable instructions by matching error detection cycles, and the commit control unit manages the order of commits to differentiate between retryable and non-retryable errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If out-of-order execution is implemented to improve processing speed, then productivity increases, but reliability deteriorates due to inaccurate distinction between retryable and non-retryable instructions
Solution Approach 1:
The patent applies preliminary action by pre-assigning count values to each instruction indicating the number of cycles from completion before error detection occurs. This allows the system to quickly determine retryability by simply comparing the pre-calculated count value with the error detection cycle, rather than performing complex analysis after an error occurs. The count value is prepared in advance for each instruction in the out-of-order execution pipeline.
Solution Approach 2:
The system implements self-service by having each instruction carry its own count value that automatically indicates its retryability status. When an error is detected, the instruction with the matching count value automatically identifies itself as retryable, eliminating the need for external control logic to analyze execution order and determine retryability. The instruction effectively serves its own retry determination function.
2Reliability
If error detection is performed in out-of-order execution, then reliability can be improved, but processing performance deteriorates due to inability to accurately identify retryable instructions
Solution Approach 1:
The patent applies preliminary action by pre-assigning count values to each instruction indicating the number of cycles from completion before error detection occurs. This allows the system to quickly determine retryability by simply comparing the pre-calculated count value with the error detection cycle, rather than performing complex analysis after an error occurs.
Solution Approach 2:
The patent uses count values as distinctive identifiers (analogous to color changes) that immediately indicate the retryability status of each instruction. When an error is detected at a specific cycle, the system can instantly identify retryable instructions by matching the error cycle with the pre-assigned count values, providing clear and immediate differentiation between retryable and non-retryable instructions without complex analysis.
3Reliability
If the system commits instructions in order to maintain coherency, then reliability improves, but productivity decreases due to waiting for earlier instructions to complete
Solution Approach 1:
The patent applies preliminary action by pre-calculating and assigning count values to instructions based on their completion timing before actual execution and error detection occur. This allows the system to maintain out-of-order execution for high throughput while using the pre-assigned count values to ensure correct retryability determination, effectively decoupling execution order from commit order.
Solution Approach 2:
The system uses feedback by continuously tracking the count values of instructions in the out-of-order execution pipeline and comparing them with error detection cycles. This feedback mechanism ensures that even though instructions are executed out of order, the system can accurately identify which instructions should be retried to maintain coherency, allowing aggressive out-of-order execution without sacrificing reliability.
Data Source
AI summary
An arithmetic processing device, includes a memory; and a processor coupled to the memory and the processor configured to: execute arithmetic processing which executes a plurality of instructions issued out of order, execute control processing which commits the plurality of instructions for which execution has been completed in order, identify, for each instruction included in the plurality of instructions, a count value which indicates a number of cycles from when execution of the instruction has been completed, and identify, among a plurality of uncommitted instructions, the instruction with the count value which matches the number of cycles in which an error is detected in the arithmetic processing as a specific instruction to be retried.