Arithmetic Processing Device Circuit Size Reduction via Statistical Bit Width Conversion
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Solution Overview
Problem
Deep neural networks face increased circuit size due to the need for a large circuit to acquire the distribution of bit positions of floating-point numbers, which occurs when converting from floating-point to fixed-point numbers, affecting the accuracy and efficiency of operations.
Innovation Solution
An arithmetic processing device with a fixed-point operator, a floating-point operator, a first converter, a statistical information acquirer, and a second converter, which converts results between fixed-point numbers of different bit widths while optimizing decimal point positions based on acquired statistical information to reduce circuit size without compromising accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a large circuit is installed to acquire the distribution of bit positions of floating-point numbers, then the accuracy of operation is improved, but the circuit size of the arithmetic processing device is increased
Solution Approach 1:
The patent extracts only the necessary statistical information (maximum and minimum bit positions) from the full distribution data of floating-point numbers. Instead of acquiring and processing the complete distribution, the system selectively extracts minimal sufficient information to determine optimal decimal point positions, thereby reducing circuit complexity while maintaining operation accuracy.
Solution Approach 2:
The patent uses a simplified copying approach where statistical information about bit position distributions is captured and stored in a compact form. Rather than implementing complex real-time analysis circuits, the system creates a simplified representation (copy) of the statistical characteristics that can be used to guide decimal point positioning decisions.
2Measurement precision
If the bit width of fixed-point numbers is increased to maintain accuracy during conversion from floating-point, then the accuracy of operation is improved, but the circuit size and data processing burden are increased
Solution Approach 1:
The patent implements dynamic bit width management where the precision of fixed-point numbers is adaptively adjusted based on the statistical characteristics of the data being processed. Instead of using a fixed large bit width for all operations, the system dynamically determines the appropriate bit width based on acquired statistical information, optimizing the balance between accuracy and circuit resource usage.
Solution Approach 2:
The patent changes the parameter of bit width based on statistical information about the input data distribution. By analyzing the maximum and minimum bit positions from statistical data, the system adjusts the bit width parameter of fixed-point representations to match the actual requirements of the computation, avoiding unnecessary use of excessive precision.
Data Source
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AI summary
An arithmetic processing device includes: a fixed-point operator that executes an operation on a fixed-point number; a floating-point operator that executes an operation on a floating-point number; a first converter that converts a result of the operation by the floating-point operator to a fixed-point number having a second bit width larger than a first bit width; a statistical information acquirer that acquires statistical information of any of the fixed-point number output by the fixed-point operator and the fixed-point number output by the first converter; and a second converter that converts, to a fixed-point number having the first bit width, the fixed-point number that has been output by the fixed-point operator or by the first converter and of which the statistical information has been acquired.