Arithmetic Processing Unit Move-In Buffer Control for Cache Miss Handling
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Solution Overview
Problem
Current processors face inefficiencies in issuing move-in requests due to the difficulty in efficiently processing successive memory access requests with cache misses within short clock cycles, leading to potential protocol errors and reduced performance.
Innovation Solution
An arithmetic processing unit with a memory access request issuance unit and a cache system that includes a tag memory, data memory, and move-in buffer control unit, which secures vacant move-in buffers and issues move-in requests based on availability and replace way usage to prevent overtake and maintain cache coherence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the processor checks the move-in buffer to determine whether a move-in request with the same index and way is already registered, then protocol errors are prevented, but processing time increases due to the predetermined processing cycle required for determination
Solution Approach 1:
The patent applies preliminary action by checking the move-in buffer status before issuing a move-in request. The processor determines in advance whether a move-in request with the same index and way is already registered, and only issues new requests when safe to do so. This prevents protocol errors caused by duplicate requests while maintaining efficient processing by avoiding unnecessary delays.
2Productivity
If the processor issues move-in requests for successive memory access requests with cache misses, then productivity improves, but the risk of protocol errors increases due to potential overtake of data responses
Solution Approach 1:
The patent implements feedback by continuously monitoring the move-in buffer status and using this information to control the issuance of new move-in requests. The processor checks whether move-in requests with the same index are already registered before issuing new requests, and adjusts its behavior based on this feedback. This maintains high productivity by allowing parallel request issuance when safe, while preventing protocol errors through real-time status monitoring.
3Reliability
If the processor waits for data response before issuing the next move-in request for the same cache block, then protocol errors are avoided, but processing efficiency decreases
Solution Approach 1:
The patent applies partial action by issuing move-in requests selectively rather than waiting for complete data responses. The processor issues multiple move-in requests in parallel when the move-in buffer status indicates it is safe to do so, without waiting for previous requests to complete. This maintains protocol coherence by checking buffer status while improving productivity through parallel request issuance, avoiding the inefficiency of sequential waiting.
Data Source
AI summary
An arithmetic processing unit includes a cache including a cache memory for storing states of data and data in a block at an index of the memory access request, a move-in buffer control unit that issues a move-in request when cache miss, and move-in buffers for registering the move-in request. The move-in buffer control unit, in response to cache miss, (a) secures a vacant move-in buffer when the vacant move-in buffer exists, (b) issues a move-in request when a move-in request having a same index as the memory access request is not registered in the move-in buffers, (c) issues the move-in request when the move-in request having the same index is registered in the move-in buffers and all ways are not used by the move-in request having the same index in the move-in buffers, and (d) releases the secured move-in buffer when all the ways are used.