Arithmetic Processing Device Register Access Inhibition
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Solution Overview
Problem
The increasing performance of arithmetic processing devices leads to higher power consumption due to larger register counts and bit widths, necessitating a method to reduce power usage without compromising performance.
Innovation Solution
Incorporating a decoding circuit, command execution circuit, register circuit, identification information holding circuit, setting circuit, and operation control circuit to inhibit register access when reading specific values, using a setting circuit to hold specific values instead of accessing registers, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of registers and bit width are increased to improve performance, then processing capability is improved, but power consumption increases
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing results of frequently executed instructions in a cache memory before they are actually needed. When the same instruction is executed again, the pre-stored result is retrieved instead of recalculating, thereby reducing power consumption while maintaining processing capability.
Solution Approach 2:
The patent uses copying by creating a cache copy of frequently accessed instruction results. Instead of accessing the full register file for every instruction, the system copies essential results to a smaller, lower-power cache memory, reducing the energy required for register access while preserving data availability.
2Reliability
If register access is performed for every reading command, then data accuracy is maintained, but power consumption increases
Solution Approach 1:
The system performs preliminary validation by checking validity flags associated with cached results before retrieval. This preliminary check ensures data accuracy without requiring full register access, reducing power consumption while maintaining reliability through flag-based verification.
Solution Approach 2:
The patent introduces validity flags as intermediaries between the cache memory and the execution unit. These flags act as mediators that verify data accuracy without requiring direct register access, enabling power-efficient retrieval while maintaining data reliability through the intermediary validation mechanism.
3Use of energy by moving object
If a cache memory is introduced to store pre-calculated results, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the register file into multiple banks, each with its own validity flags and cache associations. This segmentation allows selective access to only relevant register banks, reducing overall system complexity while enabling power-efficient operation through targeted cache utilization rather than requiring a complete redesign of the register architecture.
4Reliability
If validity flags are used to track cached results, then data reliability is maintained, but device complexity increases
Solution Approach 1:
The patent merges the validity flag storage with the existing register file structure, integrating the reliability tracking mechanism into the existing architecture rather than adding separate complex control circuits. This merging approach maintains data reliability through flag-based tracking while minimizing additional circuit complexity by reusing existing structural elements.
Data Source
AI summary
An arithmetic processing device includes: a decoding circuit configured to decode a command; a command execution circuit configured to execute the command decoded by the decoding circuit; a register circuit configured to include a plurality of registers for holding data used by the command execution circuit; an identification information holding circuit configured to store identification information for identifying a register for writing a specific value when the command is a register writing command; a setting circuit configured to hold the specific value; and an operation control circuit configured to execute inhibiting processing when the command is a register reading command, the inhibiting processing including inhibiting an access of the register by the register reading command and selecting the specific value held in the setting circuit.