Arithmetic Unit Immediate Multiplication Logic Depth Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In processing devices, such as CPUs, the execution of immediate instructions involving multiplication operations leads to performance degradation due to increased processing time and circuit complexity, especially when using multipliers with Carry Save Adders (CSA), which extend the instruction pipeline stages and increase the overall processing time.
Innovation Solution
The implementation of an arithmetic operation module within the processing device that performs multiplication operations using shift operations and addition, reducing the logic depth and enabling the execution of immediate instructions in fewer cycles by utilizing shift operation units and an add operation unit, rather than relying solely on multipliers or CSAs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a multiplier with Carry Save Adder (CSA) is used to execute immediate instructions, then the multiplication operation can be performed, but the instruction pipeline stages are extended and the overall processing time increases
Solution Approach 1:
The multiplication operation is segmented into multiple partial product calculations, where each bit of the multiplier is processed separately to generate partial products. These partial products are then added together using adders instead of a complex CSA-based multiplier, thereby reducing the critical path delay and avoiding pipeline stage extension.
2Productivity
If an immediate instruction involving multiplication is executed, then the calculation can be completed, but the circuit complexity increases
Solution Approach 1:
The multiplication circuit is segmented into a series of simpler components: AND gates for generating partial products and adders for summing them. This segmentation replaces the complex CSA-based multiplier with a more straightforward combinational logic structure, reducing overall circuit complexity while maintaining multiplication functionality.
Solution Approach 2:
The invention implements a dedicated immediate instruction execution unit that performs multiplication using a simplified approach tailored specifically for immediate instructions. Rather than using a full-featured multiplier capable of handling all instruction types, the circuit implements just enough logic (partial action) to efficiently handle immediate instructions with multiplication, thereby reducing circuit complexity.
3Adaptability or versatility
If the instruction pipeline is designed to support the longest execution time stage, then all instructions can be processed, but the maximum operation frequency is reduced
Solution Approach 1:
The multiplication operation is segmented into parallel partial product generation and sequential addition stages. This segmentation allows the critical path to be optimized by distributing the computation across multiple shorter stages rather than one long stage, thereby reducing the maximum stage execution time and enabling higher operation frequency while maintaining pipeline versatility.
Solution Approach 2:
Partial products are generated in advance during the decode stage or early execute stage, before the final addition is performed. This preliminary action allows the multiplication components to be prepared early, reducing the critical path delay in later stages and enabling the pipeline to operate at higher frequencies without sacrificing instruction processing capability.
Data Source
AI summary
There is provision of a processing device including an instruction decoder and an arithmetic unit configured to process an immediate instruction for instructing a calculation of a product of an immediate value and a constant. In response to receiving the immediate instruction, the instruction decoder generates a first shift control information and a second shift control information based on the constant. The arithmetic unit generates a first shifted value by bit-shifting the immediate value received from the instruction decoder based on the first shift control information, and a second shifted value by bit-shifting the immediate value or a complement of the immediate value based on the second shift control information. By performing an addition of the first shifted value and the second shifted value, the arithmetic unit calculates the product.