Arithmetic Processing Unit for Variable Bit Width Operations

Solution Overview

Problem

Existing processor architectures require explicit designation of data size for arithmetic operations, leading to inefficient code and increased power consumption, as they lack the ability to simultaneously perform different arithmetic operations on data of varying bit widths without additional instructions.

Innovation Solution

An information processing device with multiple input registers and adding units that perform various arithmetic operations in parallel, allowing results to be stored in output registers without explicit data size designation, thereby improving code efficiency and security by eliminating the need for explicit data size instructions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If explicit data size designation instructions are used for arithmetic operations, then processing accuracy is improved, but code efficiency deteriorates and power consumption increases

Engineering Contradiction:

Improveprocessing accuracyVSAvoidcode efficiency

Core Design Contradiction:

Measurement precisionVSProductivity

Solution Approach 1:

The arithmetic processing unit automatically determines the data size to be processed based on the input operands themselves, without requiring explicit size designation instructions. The unit performs arithmetic operations on data of varying bit widths (e.g., 8-bit, 16-bit, 32-bit, 64-bit) by self-adapting to the operand size, thereby improving code efficiency while maintaining processing accuracy

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

The arithmetic processing unit dynamically changes its operational parameters (data width, bus width, internal register allocation) based on the actual input data size. This allows the same instruction to handle multiple data sizes without requiring separate instructions for each size, thus improving code efficiency while preserving processing accuracy through appropriate parameter adaptation

Inventive Principle:

Principle #35Parameter changes

2Measurement precision

If explicit data size designation instructions are used for arithmetic operations, then processing accuracy is improved, but power consumption increases

Engineering Contradiction:

Improveprocessing accuracyVSAvoidpower consumption

Core Design Contradiction:

Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The arithmetic processing unit automatically determines the data size to be processed based on the input operands themselves, without requiring explicit size designation instructions. The unit performs arithmetic operations on data of varying bit widths (e.g., 8-bit, 16-bit, 32-bit, 64-bit) by self-adapting to the operand size, thereby improving code efficiency while maintaining processing accuracy

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

The arithmetic processing unit dynamically changes its operational parameters (data width, bus width, internal register allocation) based on the actual input data size. This allows the same instruction to handle multiple data sizes without requiring separate instructions for each size, thus improving code efficiency while preserving processing accuracy through appropriate parameter adaptation

Inventive Principle:

Principle #35Parameter changes

3Device complexity

If fixed bit width arithmetic units are used, then circuit simplicity is improved, but adaptability deteriorates

Engineering Contradiction:

Improvecircuit simplicityVSAvoiddata size adaptability

Core Design Contradiction:

Device complexityVSAdaptability or versatility

Solution Approach 1:

The arithmetic processing unit is designed to handle multiple data sizes (8-bit, 16-bit, 32-bit, 64-bit) using a single unified circuit structure. The unit universally processes various operand sizes by dynamically configuring its internal resources, eliminating the need for separate fixed-width arithmetic units for each data size while maintaining circuit simplicity

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The arithmetic processing unit dynamically adapts its operational characteristics based on the input data size. The control logic automatically configures the data path width, register allocation, and internal bus configuration according to the actual operands, enabling the same circuit to efficiently process different data widths without requiring explicit size designation instructions

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS8843542B2Information processing device, arithmetic processing method, and electronic apparatus

Publication Date: 2014.09.23 SEIKO EPSON CORP

AI summary

An information processing device includes: plural input registers including a first input register and a second input register; an added value register; a first adding unit that performs addition processing for stored data of the first input register and stored data of the second input register; a second adding unit that performs addition processing for connected data, which is obtained by connecting the stored data of the first input register and the stored data of the second input register, and stored data of the added value register; and plural output registers in which a processing result of the first adding unit or the second adding unit is stored, wherein in each of given execution cycles, the first adding unit stores a processing result of the first adding unit in any one of the plural output registers and the second adding unit stores a processing result of the second adding unit in any one of the plural output registers.