ARM Cortex-A9 L2 Cache Coherency via ACP Interface
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The ARM Cortex-A9 Multi-Processor core lacks effective solutions for memory coherency between more than four processors, leading to cache incoherency issues when tasks are distributed across multiple clusters, which hinders efficient pipeline processing.
Innovation Solution
Implementing a method that uses an Accelerate Coherency Port (ACP) to enable L2 caches to read data from L1 caches of other clusters or a shared cache, ensuring data validity and coherency between clusters, allowing collaboration between multiple processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the L1 cache of the Cortex-A9 MPcore supports write-back only mode, then write operations are simple and fast, but cache incoherency occurs between clusters when multiple processors access shared data
Solution Approach 1:
The L2 cache serves as an intermediary between multiple L1 caches across different clusters. When one cluster needs data held by another cluster, the L2 cache mediates the transfer through the ACP interface, ensuring coherency without requiring write-through mode in L1 caches. This resolves the contradiction by introducing a intermediate storage layer that maintains coherence while preserving the speed benefits of write-back mode.
Solution Approach 2:
The patent replaces the traditional mechanical bus-based inter-cluster communication with a cache-coherence protocol using the ACP (Accelerated Coherency Port) interface. This substitution enables efficient data sharing and coherency maintenance between clusters without sacrificing the write-back performance of L1 caches, as the ACP provides a dedicated coherence pathway separate from the main data bus.
2Device complexity
If the ARM Cortex-A9 series is limited to four processors per cluster, then the SCU can effectively manage memory coherency within the cluster, but collaboration between more than four processors becomes inconvenient and inefficient
Solution Approach 1:
The L2 cache is designed with multi-functionality to serve both as a cache for the local cluster and as a shared resource for inter-cluster data sharing. Through the ACP interface, it enables any number of clusters to access data held by any other cluster, making the system universally applicable to multi-processor configurations beyond the original four-processor limit while maintaining manageable complexity through standardized protocols.
Solution Approach 2:
The patent extends the coherence domain from a single cluster (one-dimensional management by SCU) to multiple clusters (multi-dimensional coordination) by introducing the L2 cache with ACP interfaces. This dimensional expansion allows processors across different clusters to collaborate efficiently, transforming the system from a single-cluster architecture to a multi-cluster scalable architecture without proportionally increasing management complexity.
3Productivity
If tasks are distributed across multiple clusters for pipeline processing, then processing throughput increases, but cache incoherency between clusters causes data validity issues
Solution Approach 1:
The L2 cache implements a feedback mechanism through the ACP interface that monitors and maintains data coherency across clusters. When processors distribute tasks across clusters, the feedback protocol ensures that data validity information is tracked and propagated, allowing pipeline processing to proceed with confidence that data remains valid and coherent across cluster boundaries, thus maintaining both throughput and reliability.
Data Source
AI summary
A method and an apparatus for implementing multi-processor memory coherency are disclosed. The method includes: a Level-2 (L2) cache of a first cluster receives a control signal of the first cluster for reading first data; the L2 cache of the first cluster reads the first data in a Level-1 (L1) cache of a second cluster through an Accelerator Coherency Port (ACP) of the L1 cache of the second cluster if the first data is currently maintained by the second cluster, where the L2 cache of the first cluster is connected to the ACP of the L1 cache of the second cluster; and the L2 cache of the first cluster provides the first data read to the first cluster for processing. The technical solution under the present invention implements memory coherency between clusters in the ARM Cortex-A9 architecture.