ARM CPU Core SME Implementation via SVE Reuse
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Solution Overview
Problem
Current implementations of ARM's Scalable Matrix Extensions (SME) instruction set require a separate SME accelerator, which is inefficient due to the need for replicating SSVE instruction hardware and additional components like load-store units and cache hierarchies.
Innovation Solution
The solution involves integrating an outer product engine and an accumulator array directly into the ARM CPU core, reusing existing SVE hardware to execute SME instructions, and employing temporal SIMD processing to reduce memory bandwidth requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a separate SME accelerator is used to process SME instructions, then matrix operation capabilities are provided, but device complexity increases due to replication of SSVE instruction hardware and additional components
Solution Approach 1:
The patent merges the SME outer product engine functionality directly into the existing SVE vector processing pipeline, eliminating the need for a separate SME accelerator. The outer product engine shares the same vector register file, load-store unit, and cache hierarchy as the SVE unit, thereby providing matrix operation capabilities without duplicating hardware components.
Solution Approach 2:
The SVE vector processing unit is designed to perform multiple functions by interpreting specific instruction patterns as outer product operations. The same vector processing hardware that executes general vector instructions can also execute SME matrix multiplication instructions by detecting the outer product instruction pattern and routing it through the appropriate computational path within the unified pipeline.
2Productivity
If a separate SME accelerator with dedicated load-store units and cache hierarchy is implemented, then matrix operation performance is improved, but power consumption increases
Solution Approach 1:
The patent combines the memory access subsystems of the SME and SVE units into a single shared infrastructure. The unified load-store unit and cache hierarchy serve both general vector operations and matrix multiplication operations, eliminating redundant memory controllers, cache memory, and interconnect structures that would otherwise be required in a separate accelerator.
Solution Approach 2:
The existing SVE memory subsystem is designed to handle both scalar and vector memory operations, and is extended to support the specific memory access patterns required by matrix multiplication. The same memory interfaces and cache structures that serve general-purpose computing are utilized for matrix operations, thereby avoiding additional power consumption from dedicated memory subsystems.
3Device complexity
If outer product engine is integrated into ARM CPU core reusing SVE hardware, then device complexity is reduced, but processing capability for matrix operations must be maintained
Solution Approach 1:
The patent implements dynamic instruction pattern recognition within the SVE pipeline to identify outer product operations. When the decoder detects an outer product instruction, the system dynamically reconfigures the execution pipeline to perform matrix multiplication using the existing vector processing units, thereby maintaining matrix operation capability without adding dedicated hardware structures.
Solution Approach 2:
The system changes the operational parameters of the existing SVE hardware to support matrix operations. By modifying the instruction interpretation logic and data flow patterns within the unified pipeline, the same physical hardware can switch between general vector processing and specialized matrix multiplication modes, maintaining full matrix operation capability through parameter reconfiguration rather than structural modification.
Data Source
AI summary
The present disclosure relates to systems and methods that add an outer product engine and an accumulator array to implement Advanced Reduced Instruction Set Computer Machine (ARM)'s scalable matrix extensions (SME) instruction set in an ARM central processing unit (CPU) core. The systems and methods reuse the existing SVE hardware already present in the ARM CPU core for executing the SME instruction set. The systems and methods of the present disclosure use temporal single-instruction multiple data (SIMD) processing an instruction over multiple cycles to reduce memory bandwidth needed in the ARM CPU core to process the SME instruction set.