ARM Core JTAG Security via Software-Controlled Blocking
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Solution Overview
Problem
Microprocessor systems based on the ARM core face security vulnerabilities due to external debug signals like JTAG, which can be exploited for unauthorized access and data manipulation, and existing solutions like one-time-programmable memory increase costs and limit reusability.
Innovation Solution
A system that includes a JTAG interface, a control signal generator, and a blocking unit to protect against external attacks by generating a control signal to block or connect the JTAG interface, using a register set up during boot image execution and multiplexers to select dummy signals when necessary, thereby preventing unauthorized access without complex mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If one-time-programmable memory is used to inactivate the debug port, then security is improved, but manufacturing cost increases and the JTAG interface cannot be reused
Solution Approach 1:
The patent changes the state of existing registers through software execution (reset handler) to control the blocking unit, rather than using hardware one-time-programmable memory. This allows the security state to be changed dynamically through parameter changes in register values, achieving both security and reusability
Solution Approach 2:
The patent creates a software-based copy of the security control function that exists in the reset handler code, rather than requiring physical OTP memory. The control logic is replicated in the boot image software, allowing the same security functionality to be achieved through executable code rather than hardware fuses
2Reliability
If one-time-programmable memory is used to inactivate the debug port, then security is improved, but the JTAG interface loses reusability
Solution Approach 1:
The patent makes the JTAG interface dynamically controllable through software execution. The blocking unit responds to control signals generated during runtime based on register values set by the reset handler, allowing the system to transition between blocked and connected states dynamically, enabling both security and reusability
Solution Approach 2:
The patent performs preliminary setup of register values in the reset handler during boot image execution, before the JTAG interface is actually needed. This preliminary action configures the blocking unit's initial state, allowing security to be established before use while maintaining the ability to change states later for reusability
3Ease of operation
If the JTAG interface is left accessible for debugging, then ease of operation is improved, but security vulnerability increases
Solution Approach 1:
The patent introduces a blocking unit as an intermediary between the JTAG interface and the processor. This mediator controls access based on control signals from the control signal generator, allowing the system to selectively block or permit JTAG access, thus protecting against unauthorized access while permitting legitimate debugging when needed
Solution Approach 2:
The patent implements a feedback mechanism where the control signal generator monitors register values and external debug request signals, then adjusts the blocking unit's state accordingly. This feedback loop ensures that the JTAG interface is blocked when security threats are detected and opened when debugging is legitimately required
Data Source
AI summary
An apparatus for protecting against external attacks for a processor based on an ARM core and a method using the same are provided. A method for protecting against external attacks for a processor based on an ARM core in accordance with an embodiment of the present invention includes: setting up a register using a reset handler, which is executed first within a boot image; generating a control signal for protecting against external attacks using any one of an external debug request signal and an output signal of the register; and blocking a JTAG interface used for JTAG communication with the processor based on the ARM core according to the control signal for protecting against external attacks.