ARM64 Floating Point Emulator via Instruction Classifier
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Solution Overview
Problem
Current Linux systems lack support for an ARM64-bit floating point emulator, limiting the ability to perform floating point computations on ARM64-bit architectures and requiring downgrading to ARM32-bit, which affects system performance and functionality.
Innovation Solution
A method is implemented to classify ARM64-bit instructions and process floating point operations using a software-based emulator, defining a floating point register and state structure, and dispatching corresponding library functions for floating point computations, allowing for emulation of ARM64-bit floating point instructions without a hardware coprocessor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a floating point coprocessor is introduced for ARM64-bit to support floating point computation, then floating point computation capability is improved, but device complexity increases and hardware cost increases
Solution Approach 1:
The patent introduces an undefined instruction handler as an intermediary layer between the ARM64-bit core and the floating point emulator. This handler intercepts floating point instructions, translates them into equivalent operations using general-purpose registers, and manages the emulation process without requiring hardware coprocessors. This resolves the contradiction by providing floating point capability through software mediation rather than hardware addition.
Solution Approach 2:
The patent creates a software-based floating point emulator that copies and replicates the functionality of a hardware floating point coprocessor. The emulator implements floating point instruction sets in software, allowing ARM64-bit processors to execute floating point operations without physical coprocessor hardware. This provides the desired functionality while avoiding hardware complexity.
2Adaptability or versatility
If a floating point emulator is implemented by software via CPU to perform floating point computation, then floating point computation capability is improved, but interruption delay increases and system real-time performance deteriorates
Solution Approach 1:
The patent implements preliminary action by pre-configuring the undefined instruction handler to recognize and intercept floating point instructions before they cause system-wide exceptions. The handler maintains pre-allocated data structures including floating point register states, exception condition records, and instruction translation tables. This preparation reduces the time required when floating point operations actually occur, minimizing interruption delays while maintaining full emulator functionality.
3Device complexity
If Linux core does not support ARM64-bit floating point emulator, then system simplicity is maintained, but floating point computation functionality is lost and ARM64-bit must be downgraded to ARM32-bit
Solution Approach 1:
The patent segments the floating point emulation functionality into a separate, modular undefined instruction handler that operates independently from the core Linux kernel. This handler is implemented as a distinct software component that can be added to existing Linux distributions without modifying the core kernel code. The segmentation allows the system to maintain kernel simplicity while providing enhanced floating point capabilities through an add-on module that works specifically with ARM64-bit architecture.
Data Source
AI summary
The present invention provides a method of implementing an ARM64-bit floating point emulator on a Linux system, which includes: running an ARM64-bit instruction on the Linux system; applying an instruction classifier to a first feature code of a machine code indicated by the ARM64-bit instruction to determine whether the ARM64-bit instruction is an ARM64-bit floating point instruction; and, if the ARM64-bit instruction is an ARM64-bit floating point instruction, applying the instruction classifier to a second feature code of the machine code indicated by the ARM64-bit instruction to determine the ARM64-bit floating point instruction to be a specific ARM64-bit floating point instruction.