Agile Ring Oscillator Timing for Usage-Adaptive Clock Cycles
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional clock generators, such as phase-locked loops (PLLs), lack flexibility in responding to environmental changes like process, voltage, and temperature variations, resulting in fixed clock cycle times that do not adapt to the varying usage patterns of circuits, leading to inefficient power usage and performance.
Innovation Solution
An agile ring oscillator (ARO) system that dynamically adjusts the cycle time of the clock by varying the number of signal inversions in its ring oscillators based on expected usage patterns, allowing for independent control of high and low phases through control words, enabling a performance-to-power ratio improvement by altering the clock period temporarily.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If conventional clock generators (PLLs) are used to provide stable clock signals, then frequency stability is improved, but adaptability to varying usage patterns and environmental changes deteriorates
Solution Approach 1:
The patent implements dynamic clock cycle time adjustment by varying the number of signal inversions in the ring oscillator based on expected circuit activity. The system transitions from static PLL-based clock generation to dynamic ARO-based generation, where the clock period can be adjusted in real-time according to usage patterns while maintaining frequency stability through controlled inversion counts.
Solution Approach 2:
The system changes the clock signal parameters (cycle time, frequency) by modifying the number of signal inversions in the ring oscillator path. By controlling the target count of signal inversions, the system can adjust the clock period to match expected circuit activity, thereby achieving both stability and adaptability.
2Device complexity
If fixed clock cycle times are used to simplify circuit design, then device complexity is reduced, but power efficiency deteriorates
Solution Approach 1:
The system introduces dynamic control of clock cycle time through the ARO controller, which adjusts the number of signal inversions based on expected circuit activity. This dynamic approach allows the circuit to consume less power during low-activity periods while maintaining simple ring oscillator architecture, thus improving power efficiency without significantly increasing complexity.
Solution Approach 2:
The system performs preliminary estimation of circuit activity using instruction decoders and activity indicators before adjusting the clock cycle time. By predicting future circuit usage patterns, the system can proactively optimize the clock period to match expected activity levels, improving power efficiency before the actual computation occurs.
3Productivity
If clock frequency is increased to improve circuit performance, then productivity is improved, but power consumption increases
Solution Approach 1:
The system dynamically adjusts clock frequency by varying the number of signal inversions in the ring oscillator based on actual circuit needs. High performance is achieved only when required by the circuit activity, while low-power mode is activated during idle periods. This dynamic adjustment resolves the contradiction by making performance and power consumption correlated with actual usage rather than being fixed.
Solution Approach 2:
The system uses periodic calibration cycles to maintain accurate frequency control while operating in dynamic mode. The ARO controller periodically updates the inversion count based on calibration data, allowing the system to switch between high-performance and low-power states efficiently, thereby achieving both productivity and power efficiency.
Data Source
AI summary
A circuit and corresponding method control cycle time of an output clock used to clock at least one other circuit. The circuit comprises an agile ring oscillator (ARO) and ARO controller. The ARO includes at least one instance of a first ring oscillator (RO) and second RO that generate high and low phases, respectively, of cycles of the output clock. The ARO controller controls durations of the high and low phases, independently, via first and second control words output to the ARO, respectively. In a present cycle of the output clock, the ARO controller effects a change to the high or low phase, or a combination thereof, in a next cycle of the output clock by updating the first or second control word, or a combination thereof, based on an indication of expected usage of the at least one other circuit in the next cycle. The change improves a performance-to-power ratio of the at least one other circuit.