Agile Ring Oscillator Clocking for Usage-Adaptive Cycle Time
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional clock generators, such as phase-locked loops (PLLs), lack flexibility in responding to environmental changes like process, voltage, and temperature variations, resulting in fixed cycle times that do not adapt to the varying usage patterns of connected circuits, leading to inefficient power usage and performance.
Innovation Solution
An agile ring oscillator (ARO) system that includes multiple ring oscillators and a controller to dynamically adjust the cycle time of the output clock based on expected usage of connected circuits, allowing for variable cycle times and improved performance-to-power ratio by altering the number of signal inversions in each cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional PLL or fixed-frequency clock generator is used, then the clock frequency is stable and predictable, but the cycle time cannot be dynamically adjusted to match varying usage patterns of connected circuits, leading to inefficient power usage
Solution Approach 1:
The patent implements dynamic cycle time adjustment by allowing the ring oscillator to vary its oscillation period based on real-time usage patterns of connected circuits. The cycle time can be extended or shortened by dynamically changing the number of inversion stages activated in the ring oscillator chain, enabling the system to adapt to varying workload demands and reduce power consumption during low-activity periods.
Solution Approach 2:
The system changes the operational parameters of the clock generator by modifying the effective number of inversion stages in the ring oscillator. By dynamically adjusting parameters such as the oscillation period and the number of active inverting gates, the system can adapt cycle time to match usage patterns while maintaining stable operation when needed.
2Use of energy by moving object
If the cycle time is extended to reduce power consumption during low-activity periods, then power efficiency improves, but the clock frequency becomes less predictable and may affect timing-critical circuits
Solution Approach 1:
The ring oscillator is divided into multiple selectable inversion stages that can be independently controlled. This segmentation allows the system to dynamically adjust the effective oscillation path by enabling or disabling specific stages, providing granular control over cycle time while maintaining a structured and predictable adjustment mechanism that doesn't compromise overall timing reliability.
Solution Approach 2:
The system uses feedback from usage pattern detection to dynamically adjust the cycle time. By monitoring the activity levels of connected circuits and adjusting the oscillation period accordingly, the system maintains timing predictability through adaptive synchronization while achieving power savings during low-activity periods.
3Adaptability or versatility
If multiple ring oscillators are used to provide different cycle times, then flexibility and adaptability improve, but the device complexity increases
Solution Approach 1:
The ring oscillator is designed with multi-functionality by incorporating multiple inversion stages that can be selectively activated. This universal design allows a single oscillator structure to provide multiple effective cycle times by dynamically enabling different combinations of inversion stages, eliminating the need for separate oscillators for each frequency requirement and reducing overall system complexity.
Data Source
AI summary
A circuit and corresponding method control cycle time of an output clock used to clock at least one other circuit. The circuit comprises an agile ring oscillator (ARO) and ARO controller. The ARO includes at least one instance of a first ring oscillator (RO) and second RO that generate high and low phases, respectively, of cycles of the output clock. The ARO controller controls durations of the high and low phases, independently, via first and second control words output to the ARO, respectively. In a present cycle of the output clock, the ARO controller effects a change to the high or low phase, or a combination thereof, in a next cycle of the output clock by updating the first or second control word, or a combination thereof, based on an indication of expected usage of the at least one other circuit in the next cycle. The change improves a performance-to-power ratio of the at least one other circuit.