Agile Ring Oscillator Clocking for Usage-Adaptive Cycle Time
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Solution Overview
Problem
Existing clock generators, such as phase-locked loops (PLLs), lack flexibility in responding to environmental changes like process, voltage, and temperature (PVT) variations, and they maintain a fixed cycle time for clock pulses.
Innovation Solution
An agile ring oscillator (ARO) circuit is employed, which includes two ring oscillators generating high and low phases of an output clock. An ARO controller adjusts the durations of these phases independently and can change them in subsequent cycles based on an indication of expected usage of other circuits, thereby altering the cycle time of the output clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a phase-locked loop (PLL) is used to generate clock signals, then frequency stability is improved, but adaptability to PVT variations and flexibility in responding to usage changes deteriorates
Solution Approach 1:
The patent implements dynamic clock cycle time adjustment by using multiple ring oscillator paths with different delay characteristics. The system transitions from static PLL-based clock generation to dynamic selection among multiple oscillator paths, allowing real-time adaptation to PVT variations and usage patterns while maintaining frequency stability through controlled phase alignment.
Solution Approach 2:
The system changes physical parameters of the clock generation by adjusting the number of inversion stages in different ring oscillator paths. By varying the effective delay through parameter selection (number of stages, enablement of specific paths), the system adapts to different operating conditions while maintaining stable clock output.
2Ease of operation
If a fixed cycle time is maintained for clock pulses, then simplicity of control is improved, but performance-to-power ratio deteriorates
Solution Approach 1:
The system implements dynamic clock cycle time adjustment by using multiple ring oscillator paths with different delay characteristics. The controller selectively enables different oscillator paths based on expected usage patterns, allowing the clock frequency to adapt dynamically while maintaining relatively simple control logic through predefined paths.
Solution Approach 2:
The system performs preliminary adjustment of clock cycle time based on predicted future usage patterns. By anticipating when circuits will be active or inactive, the controller pre-adjusts the clock frequency to optimize power consumption during upcoming operational phases, improving the performance-to-power ratio before actual usage occurs.
3Use of energy by moving object
If the clock frequency is dynamically adjusted based on expected usage, then power consumption is reduced, but timing precision and synchronization deteriorate
Solution Approach 1:
The system uses feedback mechanisms to monitor actual clock phase and timing relationships between different oscillator paths. The controller adjusts the selection and configuration of ring oscillator paths based on feedback about timing precision, ensuring that dynamic frequency adjustment does not compromise synchronization and timing accuracy.
Solution Approach 2:
The system dynamically selects among multiple pre-configured ring oscillator paths with known delay characteristics. By choosing paths with appropriate delay properties based on current timing requirements, the system maintains timing precision while adjusting frequency for power optimization. The dynamic selection ensures that timing-critical operations use paths with suitable phase characteristics.
Data Source
AI summary
A circuit and corresponding method control cycle time of an output clock used to clock at least one other circuit. The circuit comprises an agile ring oscillator (ARO) and ARO controller. The ARO includes at least one instance of a first ring oscillator (RO) and second RO that generate high and low phases, respectively, of cycles of the output clock. The ARO controller controls durations of the high and low phases, independently, via first and second control words output to the ARO, respectively. In a present cycle of the output clock, the ARO controller effects a change to the high or low phase, or a combination thereof, in a next cycle of the output clock by updating the first or second control word, or a combination thereof, based on an indication of expected usage of the at least one other circuit in the next cycle. The change improves a performance-to-power ratio of the at least one other circuit.