Array Antenna Reception With DC Offset for 1-Bit ADC Demodulation
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Solution Overview
Problem
Existing wireless communication systems face challenges in increasing capacity and processing speed without escalating power consumption and complexity, particularly due to the limitations of single-bit analog-to-digital converters (ADCs) in supporting higher-order modulation schemes.
Innovation Solution
The introduction of a wireless communication node with a large array antenna system that incorporates low-resolution ADCs, including single-bit converters, by adding a DC offset to the demodulated signals before analog-to-digital conversion, allowing for the detection of higher-order modulation formats without increasing cost or complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If single-bit ADCs are used to reduce complexity and power consumption, then device complexity and power consumption are reduced, but the ability to detect higher-order modulation formats deteriorates
Solution Approach 1:
The patent introduces a DC offset dimension to the single-bit ADC system. By adding a controllable DC offset to the analog signal before conversion, the system transforms a 1-bit quantization problem into a 2-dimensional problem (magnitude + offset), enabling higher-order modulation detection while keeping the ADC itself simple and low-power.
Solution Approach 2:
The patent changes the operating parameter of the ADC system by introducing a variable DC offset. This parameter change allows the same single-bit ADC to adapt to different modulation schemes (QPSK, 16-QAM, 64-QAM) by adjusting the offset value, thereby maintaining measurement precision without increasing ADC complexity.
2Productivity
If large array antenna systems are deployed to increase capacity and data rate, then productivity and spectral efficiency are improved, but device complexity and power consumption increase
Solution Approach 1:
The patent segments the antenna system into multiple independent receiving antenna devices, each with its own simple receiving circuit including a single-bit ADC. This segmentation allows parallel processing of multiple antenna signals, increasing overall system capacity and throughput while keeping each individual receiver unit simple and low-complexity.
Solution Approach 2:
The patent uses multiple copies of the same simple receiving circuit architecture across different antenna elements. Each copy is identical and processes signals independently, enabling scalable system design where capacity increases by simply adding more copies rather than complicating the existing design.
3Measurement precision
If high-resolution ADCs are used to support higher-order modulation schemes, then measurement precision is improved, but power consumption and cost increase
Solution Approach 1:
The patent introduces a DC offset as an intermediary element between the analog signal and the single-bit ADC. This intermediary allows the low-resolution ADC to effectively represent higher-order modulation symbols by combining the signal magnitude with the offset value, achieving high measurement precision without requiring a high-resolution (and high-power) ADC.
Data Source
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AI summary
The present disclosure relates to a wireless communication node comprising at least one array antenna (1; 1') configured to receive a radio signal, said array antenna (1; 1') comprising a plurality (M) of receiving antenna devices (2), each of said antenna devices (2) being connected to a respective receiving circuit (3) which is configured for processing said radio signal. Each receiving circuit (3) comprises a demodulator (4; 11), an analog-to-digital converter (5; 12, 13) and a decoder (6; 14), the demodulator (4; 11) being configured to receive an analog signal from the corresponding receiving antenna device (2) and to output a demodulated analog signal to said analog-to-digital converter (5; 12, 13) which outputs a converted digital signal to the decoder (6; 14). Furthermore, the node is configured for adding a direct current, DC, offset value to said demodulated analog signal wherein the combined offset values of said node follow a predetermined distribution of values, having a variance, over the analog-to-digital converters (5; 12, 13). The disclosure also relates to a method for communication over a wireless node, and an antenna arrangement.