Scalable Array Encryption Core Architecture for Flexible Throughput
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Solution Overview
Problem
High-speed hardware implementations of cryptographic algorithms face inflexibility and scalability limitations due to restrictive interface timing and the need for fixed throughput, making them difficult to use and inefficient for varying speed grades and target devices.
Innovation Solution
A scalable array encryption architecture using a plurality of encryption cores with input arbitration logic and output selection logic, allowing for flexible data encryption with a cryptographic algorithm, implemented in either fixed logic or programmable integrated circuit devices, enabling efficient processing of multiple encryption operations simultaneously.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If pipelining and unrolling are used to speed up cryptographic processing, then processing speed is improved, but interface timing becomes very restrictive and flexibility is lost
Solution Approach 1:
The patent implements a dynamic array of encryption cores where the number of active cores can be adjusted based on throughput requirements. The system transitions from static fixed-function cores to dynamic reconfigurable cores that can be selectively enabled or disabled, allowing the interface timing to adapt to different operational requirements while maintaining high processing speeds when needed.
2Area of stationary object
If a fixed number of encryption cores are used, then hardware area is reduced, but scalability to different throughputs and speed grades is limited
Solution Approach 1:
The patent divides the encryption system into multiple independent encryption cores arranged in an array, where each core can be independently controlled. This segmentation allows the system to activate only the necessary number of cores based on throughput requirements, providing scalability without proportionally increasing the active hardware area. The arbitration logic selectively enables cores to match the desired throughput level.
Solution Approach 2:
The system implements dynamic core activation where the number of active encryption cores can be adjusted in real-time based on throughput requirements. This dynamic configuration allows the same hardware footprint to support multiple throughput levels by selectively enabling or disabling cores, achieving scalability without requiring separate hardware designs for different performance levels.
3Adaptability or versatility
If discrete hardware cores are used for each encryption operation, then flexibility is improved, but system size increases
Solution Approach 1:
The patent implements universal encryption cores that can handle multiple cryptographic algorithms and operation types. Each core in the array is designed to be multi-functional, capable of performing different encryption operations by loading appropriate algorithm configurations. This universality provides the flexibility of discrete specialized cores while using a shared hardware infrastructure, reducing the total system area compared to having separate discrete hardware for each operation type.
Data Source
AI summary
A scalable and efficient array encryption architecture is provided for encrypting data with a cryptographic algorithm using a variable number of encryption cores. The architecture can be implemented as circuitry in a fixed logic device, or can be configured into a programmable integrated circuit device such as a programmable logic device (PLD). An input arbitration logic circuit may schedule timeslots within the encryption cores to maximize system bandwidth. Each one of the encryption cores may use a plurality of pipelined registers and may support simultaneous encryption operations of multiple data blocks. Each core may provide timeslot availability signals to indicate current or anticipated availability of a timeslot for processing data in that core. The same top-level design may be used for different choices of processing depth, parallelism level, and/or system throughput.