Semiconductor Array Etching with Defect Map Feedback
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Solution Overview
Problem
The shrinking of memory cell area in semiconductor devices due to shrinking isolation structure spacing leads to electrical shorts in the array region, affecting device performance.
Innovation Solution
A method of manufacturing semiconductor devices that involves forming a patterned mask structure, an etching stop layer, and an underlayer, followed by obtaining a defect distribution map to adjust process conditions, specifically adjusting the etching process or underlayer formation to reduce defects and prevent electrical shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the isolation structure spacing is shrunk to reduce memory cell area, then the memory cell area is reduced, but electrical shorts occur in the array region
Solution Approach 1:
The patent applies preliminary action by forming a mandrel structure and sacrificial layer before the final isolation structure formation. The mandrel structure is deposited and patterned first, then the sacrificial layer is formed around it, allowing precise control of the isolation structure spacing before the actual isolation structures are created. This preliminary structuring prevents electrical shorts while maintaining minimized cell area.
Solution Approach 2:
The patent uses an intermediary approach by introducing a sacrificial layer between the mandrel structure and the final isolation structures. This sacrificial layer acts as a mediator that defines the precise spacing of the isolation structures, ensuring that the spacing is sufficient to prevent electrical shorts while minimizing the overall memory cell area. The sacrificial layer is later removed, leaving the precisely spaced isolation structures.
2Ease of manufacture
If the etching process is performed without defect monitoring, then the manufacturing process is simple, but defects are generated in the array region
Solution Approach 1:
The patent implements feedback by obtaining a defect distribution map of the underlayer and using this information to adjust the etching process conditions. The defect distribution map provides real-time feedback about the quality of the underlayer, allowing the etching process parameters (such as etch rate, selectivity, or plasma conditions) to be optimized based on the actual defect locations and densities. This feedback loop reduces defects in the array region while maintaining manufacturing feasibility.
3Loss of time
If the underlayer formation process is optimized without defect analysis, then the process time is short, but defects remain in the underlayer
Solution Approach 1:
The patent applies preliminary action by obtaining the defect distribution map of the underlayer immediately after formation, before proceeding to the etching process. This early defect analysis allows the etching process to be pre-adjusted based on the known defect locations, preventing further defect generation during etching without requiring additional underlayer formation time. The defect map is obtained as a preliminary step that guides subsequent process optimization.
Data Source
AI summary
A method of manufacturing the same is provided. The method includes providing a substrate. The method also includes forming a target layer over the substrate. The method further includes forming a patterned mask structure over the target layer. In addition, the method includes forming an etching stop layer over the patterned mask structure. The method also includes forming an underlayer over the etching stop layer; and performing an etching process to pattern the target layer.