Array Fanout Pass Transistor Structure for Memory Layout
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Solution Overview
Problem
In high-density memory devices, the area required for local word line drivers becomes significant overhead due to the need for high voltage and negative voltage operating parameters, leading to increased implementation costs and space consumption.
Innovation Solution
Implementing pass transistor structures in a fanout structure for local word lines, which include a semiconductor channel body over the substrate with a contact region and an extension reaching into memory cells, allowing for efficient connection of global word lines to local word lines, reducing the need for large triple well transistors and conserving layout space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional local word line drivers are used to meet high voltage and negative voltage operating parameters, then the required voltage specifications are achieved, but the area required for implementation becomes significant overhead
Solution Approach 1:
The patent merges the local word line driver functionality directly into the fanout structure by integrating pass transistor gates with the local word line routing. This consolidation eliminates the need for separate driver circuits, reducing area while maintaining the required high voltage and negative voltage operating capabilities through shared voltage generation and distribution networks.
Solution Approach 2:
The fanout structure is designed to serve multiple functions simultaneously: it distributes global word lines to local word lines, provides voltage boosting through pass transistors, and enables both high voltage and negative voltage operations. This multi-functionality allows a single structure to replace what would traditionally require separate dedicated driver circuits for each function.
2Ease of operation
If a large number of local word line drivers are implemented, then the required word line control is achieved, but the implementation cost increases
Solution Approach 1:
By combining multiple driver functions into a single fanout structure with shared voltage generation and control logic, the patent reduces the total component count and interconnect complexity. This consolidation directly lowers implementation cost while preserving full word line control capability across all local word lines through the shared infrastructure.
3Area of stationary object
If pass transistor structures are integrated into the fanout structure, then layout space is conserved, but the structure complexity increases
Solution Approach 1:
The fanout structure is segmented into modular pass transistor units, each controlling a specific local word line. This segmentation allows the complex functionality to be broken down into repeatable, standardized building blocks that can be systematically implemented and managed, reducing the perceived complexity while achieving significant area savings.
Data Source
AI summary
A device, such as an integrated circuit including memory, includes an array of memory cells on a substrate. A row/column line, such as a local word line or local bit line, is disposed in the array. The row/column line includes a pass transistor structure comprising a semiconductor strip in a first patterned layer over the substrate. The semiconductor strip includes a semiconductor channel body, a contact region on one side of the semiconductor channel body, and an extension on another side of the semiconductor channel body, which reaches into the memory cells in the array. A select line in a second patterned layer crossing the semiconductor channel body is provided. The pass transistor structure can be implemented in a fanout structure for row/column lines in the array.