Array-Integrated Routers for Neural Core Signal Routing
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Solution Overview
Problem
Existing neural network architectures face inefficiencies in routing neural signals between cores, particularly in circuit-switched networks, which require flexible and reconfigurable connectivity without the need for address bits, and existing packet-switched solutions are area-, time-, and power-inefficient for deep learning applications.
Innovation Solution
The implementation of array-integrated upstream/downstream routers with a mesh of wires, buffers, and switches that allow for bidirectional, reconfigurable routing of neural signals between cores, using transmission gates and buffer circuitry to support both single-casting and multi-casting of data vectors across the neural network array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If packet-switched routing is used for neural network connectivity, then flexibility in routing is improved, but area, time, and power efficiency deteriorate
Solution Approach 1:
The patent replaces packet-switched routing mechanisms with circuit-switched routing mechanisms. Instead of using complex packet routing protocols and address bit processing, the invention implements dedicated circuit paths through crossbar switches and transmission gates that directly connect neural cores. This substitution eliminates the overhead of packet handling while maintaining routing flexibility through reconfigurable circuit paths.
Solution Approach 2:
The patent changes the routing paradigm from packet-based to circuit-based switching. By using circuit-switched networks with pre-established dedicated paths, the system achieves both routing flexibility and efficiency. The circuit switches can be reconfigured to create different connection patterns, providing adaptability while avoiding the area, time, and power costs of packet-switched protocols.
2Use of energy by moving object
If circuit-switched routing is implemented without address bits, then power consumption is reduced, but routing reconfigurability must be achieved through other means
Solution Approach 1:
The patent segments the routing function into multiple independent circuit switches distributed across neural cores. Each core contains local circuit switches that can be independently controlled, allowing reconfiguration of communication paths without requiring global address bit processing. This segmentation enables power-efficient circuit switching while maintaining reconfigurability through distributed control.
Solution Approach 2:
The patent implements dynamic reconfigurability through circuit switches that can change their connection states. The crossbar switches and transmission gates can be programmed to establish different circuit paths as needed, providing adaptive routing capabilities without using address bits during data transmission. The system dynamically reconfigures circuit paths to match the computational requirements of different neural network operations.
Data Source
AI summary
Array-integrated upstream/downstream routers for circuit-switched parallel connectivity are provided. A system comprises an array of neural cores having at least one dimension, a plurality of signal wires, and a plurality of routers. Each neural core comprises a plurality of ordered input wires, a plurality of ordered output wires, and a plurality of synapses, each synapse operatively coupled to one of the plurality of input wires and one of the plurality of output wires. The plurality of signal wires are disposed along each dimension of the array of neural cores. Each router is operatively coupled to one of the plurality of neural cores and to at least one signal wire along each dimension of the array of neural cores. Each of the plurality of routers is adapted to selectively route a signal from the at least one signal wire to its coupled neural core. Each of the plurality of routers is adapted to selectively route a signal from its coupled neural core to the at least one signal wire.