Array Lead Frame Package with Flip Chip Die Attach
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Solution Overview
Problem
Traditional near chip scale packages, such as dual-flat no-leads (DFN) packages, face limitations in providing sufficient input/output contacts due to small package sizes and pitch restrictions, which restricts the number of contacts that can be placed along the perimeter, and require resource-intensive wire bonding processes.
Innovation Solution
The implementation of an array lead frame coupled with flip chip bonding techniques, which provides additional input/output contacts along the package bottom area, allowing for increased contact density by using conductive bumps to attach the semiconductor die to an array lead frame, thereby avoiding wire bonding and enabling more efficient packaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional flat no-leads packaging techniques with wire bonding are used, then the package structure is simple and manufacturing is straightforward, but the number of input/output contacts is limited and the process is resource and time intensive
Solution Approach 1:
The patent replaces the mechanical wire bonding process with a flip chip die attach process using conductive bumps. Instead of mechanically bonding wires to connect die contacts to the lead frame, the invention uses pre-formed conductive bumps on the die that are reflowed to create electrical and mechanical connections directly to the lead frame contacts, eliminating the wire bonding step and reducing manufacturing complexity and time
Solution Approach 2:
The patent transitions from perimeter-only contact placement to a two-dimensional contact arrangement by placing contacts on both the perimeter and the bottom surface of the package. This dimensional expansion allows significantly more input/output contacts to be provided within the same package footprint, directly addressing the limitation of traditional flat no-leads packages
2Area of stationary object
If package size is decreased to achieve smaller footprint, then the package is more compact, but the number of contacts that can be provided along the perimeter is restricted
Solution Approach 1:
The patent utilizes the bottom surface area of the package as an additional dimension for contact placement. By positioning contacts on the bottom surface in addition to the perimeter edges, the invention effectively increases the contact capacity without increasing the package footprint, allowing small packages to provide high-density interconnects
3Adaptability or versatility
If larger semiconductor devices are incorporated to provide increased functionality, then the functional capabilities are enhanced, but the available space within the package is reduced and traditional wire bonding takes up space
Solution Approach 1:
The patent eliminates the space-consuming wire bonding process by using direct flip chip die attach with conductive bumps. This substitution removes the need for wire bonds and associated bonding hardware, freeing up valuable package volume for larger semiconductor devices while maintaining electrical connectivity
Solution Approach 2:
The patent merges the electrical connection function and mechanical support function into a single integrated structure through the lead frame contacts. The lead frame provides both the electrical pathway and the mechanical substrate for mounting the die, eliminating the need for separate wire bonds and simplifying the overall package architecture to accommodate larger devices
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the number of input/output contacts by at least 50% while maintaining the same package footprint, simplifies the manufacturing process, and allows for larger semiconductor devices by providing additional contacts along the package bottom, enhancing functional capabilities and reducing resource and time requirements.
Implementation Method 1
Each bond pad is electrically coupled to a corresponding lead of the array lead frame through a flip chip die attach
Data Source
AI summary
A small form factor near chip scale package is provided that includes input/output contacts not only along the periphery of the package, but also along the package bottom area. Embodiments provide these additional contacts through use of an array lead frame coupled to under die signal contacts through the use of flip chip bonding techniques. The array lead frame contacts are electrically isolated through the use of a partial sawing process performed during package singulation.