Array-Based Memory Addressing for Large Space Access
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Solution Overview
Problem
Segmented memory architectures require obtaining memory segment locations when subroutines are executed, limiting the ability to address large amounts of memory effectively.
Innovation Solution
An array structure is used to abstract memory addressing, allowing subroutines to execute without obtaining memory segment locations, enabling access to larger memory spaces and optimizing memory organization for performance without being constrained by conventional 32-bit address spaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If segmented memory architecture with 32-bit address space is used, then memory addressing is simple and straightforward, but the addressable memory space is limited to 4GB and requires obtaining memory segment locations during subroutine execution
Solution Approach 1:
The patent transitions from conventional 32-bit linear address space to a 40-bit address space organized as a two-dimensional array structure with 2^10 pages (1024 pages) of 2^30 bytes (1GB) each. This dimensional change allows addressing 4GB+ memory while maintaining simple indexing operations within the array bounds.
Solution Approach 2:
The patent divides the large addressable memory space into segmented pages, where each page is 1GB in size. The array structure naturally segments the address space into manageable units that can be independently addressed and organized, eliminating the need for complex memory segment location obtaining during subroutine execution.
2Speed
If conventional pointers are used to access 32-bit memory space, then memory access is direct and fast, but the ability to access large amounts of memory is limited
Solution Approach 1:
The patent extends the address space from 32-bit to 40-bit by organizing memory as a two-dimensional array with dimensions 2^10 x 2^30, enabling access to 4GB+ memory while maintaining direct array indexing for fast access without complex pointer arithmetic.
Solution Approach 2:
The array structure serves as an intermediary between the processor and the expanded memory space, providing a simplified indexing mechanism that abstracts the complexity of large address space management while enabling fast direct access to memory locations.
3Speed
If memory organization is optimized for performance, then access speed improves, but the address structure becomes complex and impacts portability
Solution Approach 1:
The array structure provides a universal interface for memory access that works consistently across different memory configurations. The same array indexing syntax can access memory regardless of the underlying organization, making the system portable while allowing performance optimization through different array implementations.
Solution Approach 2:
By organizing memory as a two-dimensional array with fixed page size (2^30 bytes) and number of pages (2^10), the patent creates a standardized memory organization that simplifies access patterns while maintaining flexibility for performance optimization through compiler or hardware-level optimizations.
Data Source
AI summary
A system and method for using an array structure to abstract the addressing of device memory allows for larger amounts of device memory to be accessed compared with using conventional pointers to access a 32 bit memory space. Additionally, the memory organization may be changed for optimal performance based on the underlying memory subsystem and characteristics of the accesses without impacting the array structure.