Array Multilayer Ceramic Capacitor for Reduced Mounting Area
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Solution Overview
Problem
The miniaturization of electronic products poses a challenge in accommodating multilayer ceramic capacitors with varying electric properties on a single printed circuit board due to limited space, restricting the miniaturization of electronic devices.
Innovation Solution
An array-type multilayer ceramic electronic component is designed with a ceramic body comprising multiple dielectric layers and internal electrodes, allowing for the formation of independent capacitor parts with different capacitance values, which are stacked and connected to reduce space requirements and enhance capacitance while maintaining efficient power management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple multilayer ceramic capacitors are mounted on a single printed circuit board, then various electric properties are achieved, but the mounting area increases
Solution Approach 1:
The patent combines multiple capacitor parts with different electric properties into a single multilayer ceramic electronic component. Multiple dielectric layers and internal electrodes are stacked to form multiple capacitor parts that are electrically connected, integrating the functions of what would traditionally require separate components. This merging approach achieves various electric properties while reducing the number of discrete components and mounting area required.
Solution Approach 2:
The patent employs a nested structure where multiple capacitor parts are stacked within a single ceramic body. Different dielectric layers and internal electrodes are arranged in a nested configuration, with each capacitor part contained within the overall structure of the single electronic component. This nesting enables multiple functional units to coexist in a compact, space-efficient manner.
2Quantity of substance
If the number of internal electrodes is increased to achieve high capacitance, then capacitance increases, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent segments the capacitor structure into multiple dielectric layers and internal electrodes that are systematically arranged. By dividing the overall capacitance requirement into multiple smaller capacitor parts stacked in series or parallel, the design achieves high total capacitance while maintaining manageable complexity through modular organization of the internal structure.
Solution Approach 2:
The patent transitions from a two-dimensional planar arrangement of electrodes to a three-dimensional stacked configuration. Multiple dielectric layers and internal electrodes are arranged in the thickness direction, utilizing the vertical dimension to increase capacitance without proportionally increasing the footprint or lateral complexity of the device.
3Volume of moving object
If electronic products are miniaturized, then product size decreases, but the space for mounting capacitors is limited
Solution Approach 1:
The patent merges multiple capacitor functions into a single integrated component, reducing the total number of discrete components required on the printed circuit board. This consolidation directly reduces the mounting space needed while maintaining the necessary capacitive functionality for miniaturized electronic products.
Solution Approach 2:
The patent utilizes the thickness direction (vertical dimension) to increase capacitance and functionality without increasing the lateral footprint. By stacking multiple dielectric layers and internal electrodes vertically, the component achieves high capacitance in a compact form factor suitable for space-constrained miniaturized devices.
Data Source
AI summary
An array-type multilayer ceramic electronic component includes a ceramic body including a plurality of first dielectric layers and a plurality of second dielectric layers, first and second internal electrodes disposed on the first dielectric layers and facing each other, third and fourth internal electrodes disposed on the second dielectric layers and facing each other, a first external electrode disposed on a first end surface of the ceramic body and connected to the first internal electrode, a second external electrode disposed on a first side surface of the ceramic body and connected to the second internal electrode, a third external electrode disposed on a second end surface of the ceramic body and connected to the third internal electrode, and a fourth external electrode disposed on a second side surface of the ceramic body and connected to the fourth internal electrode.