Array Panel Via-Hole Configuration for Aperture Ratio

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Solution Overview

Problem

Conventional array panels have a reduced aperture ratio due to source/drain metal layers occupying pixel area, limiting light utilization and display brightness.

Innovation Solution

The array panel design includes specific via-hole configurations with inverted trapezoidal cross-sections and overlapping structures to reduce the pixel area occupied by source/drain metal layers, improving the aperture ratio and display effect.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If source/drain metal layers are disposed on the island-like bridge region of the middle of pixels, then electrical connection is achieved, but the aperture ratio of the pixel is reduced

Engineering Contradiction:
Improveelectrical connectionVSAvoidaperture ratio
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent introduces a multi-layer via-hole structure (first via-hole through gate insulating layer, second via-hole through planarization layer, third via-hole through passivation layer) to achieve electrical connection in the vertical dimension rather than occupying horizontal pixel area. This dimensional transition allows the source/drain metal layers to connect through stacked via-holes, reducing their footprint on the pixel plane and thereby improving aperture ratio while maintaining reliable electrical connection.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Area of stationary object

If aperture ratio is reduced, then more pixel area is available for active elements, but light utilization rate is limited

Engineering Contradiction:
Improvepixel area for active elementsVSAvoidlight utilization rate
Core Design Contradiction:
Area of stationary objectVSUse of energy by moving object

Solution Approach 1:

The patent applies different structural configurations to different regions of the pixel. The via-holes are strategically positioned and dimensioned (with specific depth relationships where third via-hole depth > first via-hole depth) to optimize local electrical connection while minimizing impact on overall light transmission. The light-shielding layer is selectively disposed along the gate signal wire arrangement direction, providing localized shielding where needed while preserving light utilization in active pixel regions.

Inventive Principle:
Principle #3Local quality

3Device complexity

If aperture ratio is reduced, then pixel structure complexity is managed, but display brightness becomes insufficient

Engineering Contradiction:
Improvepixel structureVSAvoiddisplay brightness
Core Design Contradiction:
Device complexityVSIllumination intensity

Solution Approach 1:

The patent segments the electrical connection path into multiple discrete via-holes (first, second, and third via-holes) distributed across different insulating layers. This segmentation allows each via-hole to be optimized independently for its specific function while collectively achieving the overall electrical connection. The segmented structure reduces the concentrated area occupation compared to a single large connection region, thereby improving aperture ratio and display brightness while managing structural complexity through modular design.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10838272B2Array panel
Publication Date: 2020.11.17 WUHAN CHINA STAR OPTOELECTRONICS TECH CO LTD
  • US10838272B2 patent drawing
  • US10838272B2 patent drawing
  • US10838272B2 patent drawing

AI summary

An array panel includes at least: a first via-hole disposed on a surface of the interlayer insulating layer; a second via-hole disposed on a surface of the planarization layer; a third via-hole disposed on a surface of the passivation layer; a pixel electrode layer; a light-shielding layer; wherein the third via-hole partially overlaps the first via-hole or an interconnect formed by connecting both ends of the active layer on the first via-hole is parallel to an arrangement direction of the gate signal wire.