Array and Peripheral Area Masking for Semiconductor Memory
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Solution Overview
Problem
As design rules shrink, achieving well-defined boundaries for sense amplifiers and arrays in semiconductor memory devices becomes challenging, leading to decreased error margins and increased risks of shorts, which affect effective electrical connections and conductivity.
Innovation Solution
Concurrently forming multiple masks in the array and peripheral active areas and placing etch stop spacers to create defined boundaries, reducing over-etching and increasing the surface area for sense amplifier landing margins, thereby enhancing electrical connections and conductivity without additional processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If design rules are shrunk to increase integration density, then device capacity increases, but boundary definition between sense amplifiers and arrays deteriorates leading to shorts and decreased error margins
Solution Approach 1:
The patent divides the masking process into separate array active area masks and peripheral component active area masks formed at different stages. This segmentation allows independent optimization of boundary definitions for sense amplifiers and memory arrays, preventing shorts while maintaining high integration density through controlled shrinkage of design rules.
Solution Approach 2:
The patent forms array active area masks before forming peripheral component active area masks. This preliminary action establishes the boundary for sense amplifiers first, preventing subsequent over-etching into the array area when peripheral components are processed, thus maintaining manufacturing precision despite design rule shrinkage.
2Device complexity
If conventional single-mask etching is used, then process simplicity is maintained, but over-etching occurs reducing sense amplifier landing margins and electrical connections
Solution Approach 1:
The patent segments the etching process into multiple stages with separate masks: array active area masks for defining sense amplifier boundaries, and peripheral component active area masks for subsequent etching. This prevents over-etching that would otherwise reduce landing margins and compromise electrical connections, while the modular approach keeps process complexity manageable.
Solution Approach 2:
The patent introduces array active area masks as intermediary protective structures during peripheral component etching. These masks act as mediators that prevent the etchant from reaching and damaging the sense amplifier regions, ensuring reliable electrical connections without requiring complete redesign of the etching chemistry or equipment.
3Length of moving object
If design rules are reduced, then device miniaturization is achieved, but error margins decrease increasing short risks
Solution Approach 1:
The patent applies different mask qualities and formation stages to different regions: array active area masks with specific thicknesses and materials for sense amplifier regions, and peripheral component masks for other areas. This local differentiation maintains adequate error margins in critical boundary regions while allowing overall device miniaturization through reduced design rules.
Solution Approach 2:
The patent forms array active area masks in advance before peripheral component processing. This preliminary action establishes protective boundaries that prevent subsequent etching steps from encroaching on sense amplifier regions, maintaining error margins even as overall device dimensions are reduced through design rule shrinkage.
Data Source
AI summary
The present disclosure includes apparatuses and methods related to array and peripheral area masking. An example method comprises concurrently forming an array active area mask in an array active area and a peripheral component active area. The method further comprises forming a peripheral component active area mask in the peripheral component active area. The method further comprises concurrently forming etch stop spacers using the array active area mask in the array active area and the peripheral component active area. The method further comprises etching a portion of the peripheral component active area to open peripheral component conductive contact vias using the peripheral component active area mask together with the formed etch stop spacers in order to reduce over-etch of an opening to a device well while increasing surface area opening to a peripheral component conductive contact.