Array Processor Delay Adjusting Circuit for Critical Path Optimization
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Solution Overview
Problem
Array-type processors face challenges in adjusting cycle time for parallel processing and improving operation efficiency due to varying critical path delays, making it difficult to operate at high speeds and efficiently process multiple data paths simultaneously.
Innovation Solution
An array-type processor with a delay adjusting circuit that adjusts the clock signal delay based on configuration information, allowing the clock cycle length to be changed dynamically, thereby synchronizing data path operations and optimizing processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed clock cycle is used in array-type processors, then the processor can operate reliably, but the maximum operating frequency is limited by the longest critical path delay
Solution Approach 1:
The patent applies dynamics by making the clock cycle period variable rather than fixed. The clock generating circuit dynamically adjusts the clock cycle period based on the actual critical path delay of the currently active data path configuration, allowing the processor to operate at the maximum possible frequency for each configuration while maintaining reliability.
Solution Approach 2:
The patent changes the parameter of clock cycle period from a fixed value to a variable value that adapts to different data path configurations. The delay adjusting circuit measures or estimates the critical path delay and adjusts the clock cycle period parameter accordingly, enabling the system to optimize operating frequency for each specific configuration.
2Reliability
If the clock cycle is extended to accommodate the longest critical path, then all data paths can operate reliably, but data paths with shorter critical paths experience processing inefficiency
Solution Approach 1:
The patent applies local quality by providing different clock cycle periods tailored to different data path configurations. Instead of using a uniform clock cycle for all configurations, the system adjusts the clock cycle period locally for each configuration based on its specific critical path delay, ensuring that each data path operates with an optimally matched clock period.
Solution Approach 2:
The system dynamically adjusts the clock cycle period to match the actual needs of each data path configuration. The delay adjusting circuit continuously or periodically updates the clock period based on the current configuration's critical path delay, allowing short-critical-path configurations to operate faster without compromising the reliability of long-critical-path configurations.
3Productivity
If the clock cycle is shortened to improve processing speed, then processing efficiency increases, but the processor cannot reliably handle data paths with longer critical path delays
Solution Approach 1:
The patent changes the clock cycle period parameter dynamically based on the critical path delay of the active configuration. When a configuration with a short critical path is active, the system shortens the clock cycle period to increase processing speed. When a configuration with a long critical path becomes active, the system extends the clock cycle period to ensure reliable operation, thus adapting the parameter to the current operational requirements.
4Adaptability or versatility
If sequential processing is used in microprocessors, then application programs can be flexibly switched, but the processing capability cannot be improved for large quantities of data
Solution Approach 1:
The patent applies segmentation by dividing the processing system into multiple parallel data paths, each capable of independent operation. The array-type processor architecture segments the processing capability into multiple concurrent execution units, allowing large quantities of data to be processed in parallel while maintaining the ability to flexibly switch between different application programs through configurable data path settings.
Data Source
AI summary
Disclosed is an array-type processor including a data path unit in which a plurality of processor elements are arranged in an array; a state-transition management unit that stores information for controlling changeover of data paths; and a delay adjusting circuit that adjusts delay of the input clock signal based upon information output from the state-transition management unit, and provides the delay-adjusted clock signal to the data path unit. The delay adjusting circuit has a delay control information memory and a programmable delay. The delay control information memory stores a plurality of items of delay control information, delay control information is read out using a configuration number supplied from the state-transition management unit as an address, and the delay control information is applied to the programmable array. The programmable delay delays the input clock signal by a delay time specified by the delay control information and provides the delayed clock signal to the data path unit.