Array Processor Parallel Image Scaling with Pre-calculated Parameters

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Solution Overview

Problem

Existing image scaling technologies fail to fully utilize parallelism, resulting in low efficiency and time-consuming parameter recalculations during the image scaling process.

Innovation Solution

A processor and method that utilize an array processor with N processing elements to calculate channel values of a target image in parallel, using a control circuit to send calculation control signals and an off-chip memory to store the original image, with on-chip caches for improved data access speed, and a parameter transfer circuit to determine necessary parameters for scaling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a general-purpose processor is used for image scaling, then the processor can perform scaling operations, but the parallelism is low and efficiency is poor

Engineering Contradiction:
Improveimage scaling efficiencyVSAvoidprocessor architecture complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The processor is divided into multiple independent processing elements (PEs) that can operate in parallel. Each PE can process different pixels or different channels of the image simultaneously, thereby increasing the parallelism and efficiency of image scaling operations without requiring a completely new architectural paradigm.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The processing elements are designed with universal functionality to handle various scaling operations. The same PE architecture can process different image data, apply different scaling factors, and handle multiple channels (RGB, grayscale, etc.), making the system versatile while maintaining high parallelism.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If parameters are repeatedly calculated during image scaling, then the scaling can be performed, but the process becomes time-consuming

Engineering Contradiction:
Improvescaling operation speedVSAvoidparameter calculation time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

Scaling parameters such as width scaling factor and height scaling factor are pre-calculated and stored in registers or lookup tables before the actual image processing begins. This preliminary preparation eliminates the need for repeated parameter calculations during the scaling operation, significantly reducing processing time and improving throughput.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The processing elements are designed to automatically use pre-computed parameters without requiring repeated calculation. The system leverages the pre-prepared parameter data to execute scaling operations efficiently, allowing the processing to proceed at full speed without time-consuming recalculations.

Inventive Principle:
Principle #25Self-service

3Productivity

If an array processor with N processing elements is used, then parallelism is significantly improved, but the device complexity increases

Engineering Contradiction:
Improveparallel processing capabilityVSAvoidarray processor structure
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

Each processing element in the array is designed with standardized, simplified local functionality. Rather than creating a complex monolithic processor, each PE has uniform, straightforward circuitry that handles a specific portion of the image data. This modularity allows for easier design and implementation while achieving high parallelism through the collective action of multiple simple units.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS10922785B2Processor and method for scaling image
Publication Date: 2021.02.16 APOLLO INTELLIGENT DRIVING (BEIJING) TECHNOLOGY CO LTD
  • US10922785B2 patent drawing
  • US10922785B2 patent drawing
  • US10922785B2 patent drawing

AI summary

A processor and method for scaling an image are disclosed. A specific embodiment of the processor includes: an off-chip memory, a communication circuit, a control circuit, and an array processor, wherein: the off-chip memory is configured for storing a to-be-scaled original image; the communication circuit is configured for receiving an image scaling instruction; the control circuit is configured for executing the image scaling instruction, and sending a calculation control signal to the array processor; and the array processor is configured for calculating in parallel channel values of N channels in a target pixel using N processing elements in the array processor under the control of the calculation control signal based on a width scaling factor, a height scaling factor, and channel values of N channels in extracted pixel data. The embodiment has improved the processing speed of an image scaling operation.