Reconfigurable Array Processor Sorting Architecture

The array processor is divided into multiple processing elements (PEs), each capable of independent comparison operations. This segmentation allows parallel processing of multiple data elements simultaneously, significantly improving sorting efficiency while distributing the computational complexity across multiple simple units rather than requiring a single complex sorting unit.

The patent introduces a hierarchical organization with multiple levels of PEs arranged in a tree-like structure. This adds a dimensional aspect to the sorting process, where data flows through multiple levels of comparison stages. Each level performs comparisons on different subsets of data, transforming the sorting problem from a single-dimensional sequential process into a multi-dimensional parallel process that achieves O(log n) depth complexity.

The patent combines multiple sorted streams from different PE subsets into a single sorted output stream through a merging mechanism. This merging approach allows parallel PEs to work independently on their respective data subsets while the combining logic ensures the final output is globally sorted. The merging operation achieves parallel speedup while keeping individual PE complexity low, as each PE only needs to handle local comparisons and pass results to the merging stage.

The load streaming unit acts as an intermediary that manages data distribution to PEs and collects results from them. This mediator component simplifies the complexity by providing a centralized coordination point that handles the intricate data routing and synchronization between multiple PEs, allowing the PEs themselves to remain simple comparison units without requiring complex inter-PE communication logic.