Array QFN Package I/O Density via Lead Frame Segmentation

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Solution Overview

Problem

Conventional QFN packages have a limited number of I/O connections, which necessitates reducing lead pitches to increase them, leading to signal interference and complicating the manufacturing process.

Innovation Solution

The development of an array QFN package where multiple semiconductor packages are attached to a lead frame, with IC dice electrically connected to the leads and encapsulated in a mold compound, allowing for a greater number of exposed I/O terminals without reducing lead pitches, and a method involving existing assembly processes to form these packages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the number of I/O connections on a QFN package is increased by reducing lead pitches, then more connections are achieved, but signal interference increases and manufacturing complexity increases

Engineering Contradiction:
Improvenumber of I/O connectionsVSAvoidsignal interference
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent transitions from a conventional periphery-arranged lead layout to a three-dimensional array configuration where leads are arranged in multiple layers and dimensions. This dimensional change allows significantly more I/O connections to be achieved without reducing the pitch between adjacent leads, thereby maintaining signal integrity while increasing connection density.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The lead frame is segmented into multiple independent lead groups arranged in an array configuration, with each lead serving as an independent connection point. This segmentation allows for optimized spacing between leads while achieving a higher total number of connections through the array structure rather than a continuous periphery arrangement.

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If the number of I/O connections on a QFN package is increased by reducing lead pitches, then more connections are achieved, but manufacturing complexity increases

Engineering Contradiction:
Improvenumber of I/O connectionsVSAvoidmanufacturing process complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

By arranging leads in a three-dimensional array rather than a two-dimensional periphery, the patent achieves higher connection density without requiring proportionally higher manufacturing precision. The array structure provides natural spacing that simplifies alignment and assembly processes compared to densely packed periphery leads.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Quantity of substance

If lead pitches are reduced to increase I/O connections, then more connections are achieved, but cross-talk and signal interference increase

Engineering Contradiction:
Improvenumber of I/O connectionsVSAvoidcross-talk and signal interference
Core Design Contradiction:
Quantity of substanceVSObject-generated harmful factors

Solution Approach 1:

The array configuration distributes leads across multiple dimensions and layers, increasing the effective spacing between adjacent leads compared to a compact periphery arrangement. This increased spacing reduces electromagnetic coupling and cross-talk between signals while maintaining a high total number of connections.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS7531383B2Array quad flat no-lead package and method of forming same
Publication Date: 2009.05.12 NORTH STAR INNOVATIONS
  • US7531383B2 patent drawing
  • US7531383B2 patent drawing
  • US7531383B2 patent drawing

AI summary

An array QFN package (10) includes a first semiconductor package (12) and a lead frame (14) having a plurality of leads (16). A first IC die (22) is attached on a first side to the first semiconductor package (12) and is electrically connected to the leads (16) of the lead frame (14). A mold compound (30) encapsulates the first IC die (22), a portion of the first semiconductor package (12) and a portion of the leads (16) such that a plurality of I/O terminals (32) on the semiconductor package (10) is exposed.