Array Sensor Memory Integration for Layout Area Reduction
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Solution Overview
Problem
Conventional array sensors face challenges with increased layout area and setup/hold time violations due to the distribution of memories around the sensing chip, which complicates the design and manufacturing process.
Innovation Solution
The integration of a memory array below or between the sensing units in the array sensor, with an access module to selectively read sensing values and access memory units, allowing for efficient data storage and processing while reducing layout area and manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If memories are disposed around the sensing array, then the sensing chip can perform operations, but the layout area of the sensing chip is increased
Solution Approach 1:
The patent merges the memory array with the sensing array by disposing memory units at the same location as sensing units or between adjacent sensing units. This overlay configuration allows both sensing and memory functions to coexist in the same physical space, effectively reducing the overall layout area while maintaining full operational capability of both components.
Solution Approach 2:
The patent utilizes the vertical dimension by disposing memory units below the sensing units or in the space between adjacent sensing units. This three-dimensional arrangement allows memory and sensing functions to occupy different vertical layers or spatial zones, enabling both components to function simultaneously without increasing the planar layout area.
2Ease of manufacture
If memories are disposed around the sensing array, then the sensing chip can perform operations, but the difficulty of layout is increased due to setup/hold time violations
Solution Approach 1:
By merging the memory array with the sensing array in the same physical location, the patent simplifies the layout structure and reduces the number of separate signal paths. This integration eliminates the need for complex interconnections between separately disposed memory and sensing arrays, thereby reducing setup/hold time violations and lowering layout complexity.
Solution Approach 2:
The patent applies local quality by allowing different units (sensing or memory) to occupy the same physical location based on local functional requirements. This localized functional assignment simplifies the overall layout by eliminating the need for global memory placement around the sensing array, reducing signal path complexity and associated timing violations.
3Quantity of substance
If memory capacity is increased, then more data can be stored, but the layout area of the sensing chip is increased
Solution Approach 1:
The patent merges memory and sensing functions in the same physical space, allowing memory units to be disposed at the same location as or between sensing units. This integration enables increased memory capacity without proportionally increasing the layout area, as memory and sensing components share the same physical footprint.
Solution Approach 2:
By utilizing the vertical dimension and disposing memory units below or between sensing units, the patent enables increased memory capacity within the same planar layout area. This three-dimensional arrangement allows more memory units to be packed into the available space without increasing the chip's footprint.
Data Source
AI summary
An array sensor is provided. The array sensor includes a sensing array, a memory array, and an access module. The sensing array includes a plurality of sensing units, wherein each of the sensing units includes a sensing electrode. The memory array includes a plurality of memory units, wherein each of the memory units is disposed below the corresponding sensing unit or between the two adjacent sensing units. The access module selectively reads a sensing value of the sensing electrode of the sensing unit to provide a sensing output, or accesses the memory unit.