Array Substrate Alignment Circuit via Layered Transfer Lines
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Solution Overview
Problem
The alignment circuit on array substrates for liquid crystal displays is prone to short-circuiting due to etching residue, which interferes with light alignment and affects the display's operational efficiency.
Innovation Solution
The array substrate design includes short-circuited bars and transfer lines on different metal layers, with each metal layer covered by a protection layer to prevent short-circuiting, allowing for effective light alignment and ensuring that the alignment circuit can apply voltage correctly, even when via holes are present along the short-circuited bars.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If transfer lines are disposed on the same metal layer to simplify manufacturing, then manufacturing complexity is reduced, but short-circuiting occurs due to etching residue between adjacently disposed transfer lines
Solution Approach 1:
The patent applies dimensional separation by disposing adjacently arranged transfer lines on different metal layers (first metal layer and second metal layer) instead of the same layer. This vertical separation in the Z-dimension eliminates the short-circuiting problem caused by etching residue while maintaining manufacturing feasibility through standard multi-layer PCB processes.
2Adaptability or versatility
If alignment circuits are disposed on the array substrate to enable light alignment, then liquid crystal alignment capability is improved, but short-circuiting occurs due to etching residue affecting circuit operation
Solution Approach 1:
The alignment circuits are implemented using transfer lines disposed on different metal layers, creating vertical separation that prevents etching residue-induced short-circuits. This enables reliable light alignment functionality while maintaining circuit stability through the multi-layer structural design.
3Reliability
If multiple transfer lines are adjacently disposed to connect short-circuited bars, then electrical connection reliability is improved, but short-circuiting occurs due to etching residue between adjacent lines on the same layer
Solution Approach 1:
Adjacent transfer lines are distributed across different metal layers (first and second metal layers) rather than being co-planar. This vertical stratification eliminates the harmful interaction of etching residue between adjacent lines while preserving electrical connection reliability through proper via connections between layers.
Data Source
AI summary
The present application discloses an array substrate and a display panel. The array substrate includes a display region and a peripheral region; a plurality of pixels formed in the display region; a plurality of alignment circuit formed in the peripheral region for implementing alignment for the liquid crystals within the pixels; where the alignment circuits include first bonding pads and a plurality of short-circuited bars, each of the plurality of short-circuited bars is electrically connected to the first bonding pads through transfer lines, and any two of the transfer lines adjacently disposed are disposed on different metal layers.