Array Substrate Alignment Mark Detection via Segmented Via Holes
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Solution Overview
Problem
The alignment mark on conventional array substrates is prone to failure due to inconsistent gradients of via hole sidewalls, leading to detection failures during the alignment process.
Innovation Solution
An array substrate with an alignment mark in the source-drain electrode layer connected through a first via hole in the gate and common electrode layers, and a detection hole in the passivation and pixel electrode layers, allowing for normal detection with reduced risk of sidewall breaks and improved electron absorption efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple dry-etching steps are used to form via holes through gate insulation layer and etch barrier layer, then the alignment mark can be connected to common electrode, but the sidewall gradient inconsistency causes pixel electrode breaks and detection failures
Solution Approach 1:
The patent divides the via hole formation process into two separate stages: first forming a contact hole through the gate insulation layer, then forming a via hole through the etch barrier layer. This segmentation allows each etching step to have optimized parameters, ensuring consistent sidewall gradients and preventing pixel electrode breaks while maintaining alignment mark connectivity.
Solution Approach 2:
The patent performs preliminary protective actions by forming a protective film on the pixel electrode before etching, and by carefully controlling the etching depth and sidewall angle in advance. This preliminary protection prevents pixel electrode breaks during the etching process and ensures the alignment mark remains intact for reliable detection.
2Strength
If via hole size and sidewall gradient are strictly controlled, then pixel electrode break can be avoided, but the etching process becomes difficult to control and alignment mark failure still occurs
Solution Approach 1:
The patent applies different etching parameters for different regions: the contact hole etching uses parameters optimized for gate insulation layer, while the via hole etching uses parameters optimized for the etch barrier layer. This local quality approach allows each region to have optimal etching conditions, maintaining pixel electrode integrity while improving overall process controllability.
Solution Approach 2:
The patent adds a dimensional solution by introducing a protective film layer and using angled sidewall control. Instead of relying solely on via hole dimensions, the solution incorporates the protective film thickness and sidewall angle as additional control dimensions, making the etching process more controllable while preventing pixel electrode breaks.
3Measurement precision
If alignment mark is formed on pixel electrode layer, then detection can be performed, but the complex via hole structure causes breaks and detection failures
Solution Approach 1:
The patent extracts the alignment mark formation from the problematic multi-layer via hole structure. By forming the alignment mark on the pixel electrode layer after the via holes are completed, and by using the segmented via hole approach, the detection function is preserved while the complex structure-induced failures are eliminated.
Solution Approach 2:
The patent provides beforehand cushioning by forming a protective film on the pixel electrode before etching the via holes. This protective layer acts as a cushion that prevents pixel electrode breaks during the etching process, ensuring the alignment mark remains intact and detection can proceed without failures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the likelihood of alignment mark failure and enhances detection sensitivity by simplifying the etching process to one dry-etching step and using a more efficient electron-absorbing material, improving alignment accuracy.
Implementation Method 1
a metal region in the alignment mark region will absorb electrons emitted by the detection device to form an electric current
Data Source
AI summary
An array substrate and a display device incorporating the array substrate are disclosed. The array substrate includes an alignment mark formed in a source-drain electrode layer, and a detection hole formed in a region in a pixel electrode layer and a passivation layer that corresponds to the alignment mark, such that normal detection of the alignment mark can be carried out by irradiating an electronic beam into the detection hole. The structure of the array substrate reduces the likelihood of detection failures.