Array Substrate Alignment Mark for Source-Drain Electrode Precision
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Solution Overview
Problem
In the manufacturing of thin film transistor liquid crystal display panels, precise alignment of source and drain electrodes with the active layer during rework processes is challenging, leading to misalignment and abnormal transistor operations, which can result in product failure.
Innovation Solution
An array substrate with alignment marks formed in the same layer as the active layer in the non-display region, allowing for precise alignment of the source and drain electrodes with the active layer during re-fabrication, using a method that includes forming a semiconductor layer and an ohmic contact layer, and additional alignment marks for enhanced precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If alignment marks are formed in the gate electrode metal layer, then the mask can be aligned with the gate electrode, but the source and drain electrodes cannot be precisely aligned with the active layer
Solution Approach 1:
The alignment mark is moved from the gate electrode metal layer (lower dimension/layer) to the same layer as the active layer (higher dimension/layer). This dimensional change in the alignment mark's position enables direct alignment with the source and drain electrodes during rework, achieving precise alignment between the source/drain electrodes and the active layer without relying on indirect alignment through the gate electrode.
2Ease of manufacture
If the source and drain electrodes are re-fabricated using conventional alignment methods, then the rework process can be completed, but misalignment between source/drain electrodes and active layer occurs
Solution Approach 1:
The alignment mark serves as an intermediary reference feature in the same layer as the active layer. During rework, this alignment mark mediates the alignment process between the mask and the active layer, enabling precise positioning of the source and drain electrodes relative to the active layer without direct physical contact or complex multi-layer alignment procedures.
3Reliability
If precise alignment is achieved, then transistor performance is ensured, but the alignment process becomes more complex
Solution Approach 1:
The alignment mark is formed in the same layer as the active layer during the same manufacturing process, making it self-aligned. This self-service approach eliminates the need for complex multi-step alignment procedures, as the alignment mark automatically provides the correct reference position for the source and drain electrodes, ensuring transistor reliability while simplifying the alignment process.
Data Source
AI summary
Embodiments of the disclosure provide an array substrate and a manufacture method thereof. The array substrate comprises a display region and a non-display region, the display region comprises a transistor, the transistor comprises a source electrode, a drain electrode and an active layer, the source electrode and the drain electrode are provided on the active layer and are respectively provided at two ends of the active layer. The non-display region is provided with an alignment mark, the alignment mark is provided in a same layer as the active layer and is configured for aligning the source electrode and the drain electrode with the active layer in the case of re-fabricating the source electrode and the drain electrode.