Array Substrate Antistatic Pathways for High PPI Displays
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Solution Overview
Problem
In display panel manufacturing, electrostatic breakdown due to static electricity accumulation causes damage to metal wires and passivation layers, especially with increasing Pixel Per Inch (PPI) leading to smaller wire sizes and gaps, making it difficult to prevent electrostatic discharge before forming antistatic devices.
Innovation Solution
The array substrate design includes a base substrate with a conductive layer, passivation layers with through-holes, and light-shielding layers with parallel metal wires, where the metal wires are electrically connected through these holes to transfer electrostatic charges to the conductive layer, preventing discharge and damage during manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the size of pixels, line width of metal wires, and gap between adjacent metal wires are reduced to achieve higher PPI, then the display resolution is improved, but the risk of electrostatic breakdown and damage to metal wires increases
Solution Approach 1:
The patent forms antistatic devices including through-holes in passivation layers before completing the metal wire structure. This preliminary action creates electrostatic discharge pathways in advance, preventing charge accumulation that would otherwise damage the fine metal wires during subsequent manufacturing processes.
Solution Approach 2:
The patent introduces passivation layers with through-holes as intermediary structures between the metal wires and the conductive layer below. These through-holes serve as mediators that provide controlled electrostatic discharge pathways, protecting the fragile metal wires from direct electrostatic breakdown while maintaining the high-resolution display structure.
2Ease of manufacture
If traditional antistatic devices are formed after metal wires are created, then the manufacturing process is simplified, but damage to wires from static electricity accumulation occurs before antistatic protection is in place
Solution Approach 1:
The patent reverses the conventional sequence by forming the through-holes in passivation layers before completing the metal wire structure. This preliminary creation of electrostatic discharge pathways ensures protection is in place before wires are vulnerable to static damage during subsequent processing steps.
Solution Approach 2:
The patent establishes antistatic protection mechanisms in advance by creating through-holes that can dissipate static charges before they accumulate to dangerous levels. This beforehand cushioning prevents wire damage during manufacturing operations that would otherwise generate harmful electrostatic charges.
3Reliability
If multiple thin film transistors or leads are used as antistatic devices, then static electricity can be released, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent extracts the antistatic function from complex transistor structures and implements it through simpler through-holes in passivation layers. By removing unnecessary structural complexity and retaining only the essential electrostatic discharge capability, the solution achieves reliability with reduced device complexity.
Solution Approach 2:
The patent uses simple through-hole structures rather than complex, expensive transistor-based antistatic devices. These through-holes serve as disposable or temporary structures that fulfill the antistatic function during manufacturing without requiring the complexity of fully functional transistors or leads.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively transfers and dissipates electrostatic charges, preventing damage to metal wires and passivation layers, enhancing manufacturing yield and reliability, especially for high PPI displays, and simplifies the design and process margin.
Implementation Method 1
the metal wires are electrically connected through these holes to transfer electrostatic charges to the conductive layer
Data Source
AI summary
An array substrate and an array substrate fabrication method are provided. The array substrate comprises a base substrate, a first conductive layer, a first passivation layer including a plurality of first through-holes. a light-shielding layer including a plurality of first metal wires arranged in parallel, a second passivation layer including a plurality of second through-holes, and a first metal layer including a plurality of second metal wires arranged in parallel and one-to-one corresponding to the plurality of first metal wires. The first metal wire is electrically connected to the first conductive layer through at least one first through-hole, and the second metal wire is electrically connected to the corresponding first metal wire through at least one second through-hole. The array substrate includes a display region and a non-display region, and the first through-holes and the second through-holes are formed at the non-display region of the array substrate.