Array Substrate Aperture Insulation Protrusion
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Solution Overview
Problem
In array substrates used in display devices, local thinning of the insulation layer between conductive layers due to semiconductor layer steps can lead to dielectric breakdown, compromising the reliability of the array substrate and the display device.
Innovation Solution
The array substrate configuration includes a semiconductor layer with an aperture between the first and second electrodes, a first insulating layer covering these electrodes, and a gate electrode disposed above the insulating layer, which helps in protecting the channel regions of the transistors from etching damage and reduces the risk of dielectric breakdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If thin-film transistors are arranged close to each other to increase device density, then productivity and area utilization are improved, but the insulation layer becomes locally thin due to semiconductor layer steps, leading to dielectric breakdown and reduced reliability
Solution Approach 1:
The patent applies local quality by forming a protrusion in the insulation layer at the step portion where the semiconductor layer has higher elevation. This protrusion locally reinforces the insulation layer thickness at the critical step region, while maintaining the overall thin profile elsewhere. The protrusion is formed by selective deposition or planarization processes that target only the step portion, creating non-uniform local thickness distribution that prevents dielectric breakdown at high-density transistor arrangements.
2Device complexity
If the insulation layer is made thinner to reduce device thickness, then device complexity and size are reduced, but dielectric breakdown risk increases due to insufficient insulation at step portions
Solution Approach 1:
The patent maintains overall thin device profile while locally thickening the insulation layer at step portions through the protrusion structure. The insulation layer has varying thickness: thin over flat semiconductor regions to reduce overall device thickness, and thick at step portions via protrusions to prevent dielectric breakdown. This spatially differentiated thickness distribution resolves the contradiction between thinness and reliability.
3Shape
If conventional planarization is applied to the insulation layer, then surface flatness is improved, but the channel regions become exposed and susceptible to etching damage
Solution Approach 1:
The patent applies selective planarization that creates protrusions only at step portions rather than uniform planarization across the entire insulation layer. The protrusions are formed by controlled deposition or chemical mechanical polishing that targets elevated regions. This local planarization achieves surface flatness at critical step areas while preserving the insulation layer's protective coverage over channel regions, preventing etching exposure.
Solution Approach 2:
The protrusions are formed in advance before subsequent etching or processing steps. By pre-forming the protrusion structure that covers the step portion, the channel regions are protected from etching damage before the etching process occurs. The protrusion acts as a preliminary protective barrier that prevents harmful etchant contact with exposed channel regions.
Data Source
AI summary
According to one embodiment, an array substrate includes a semiconductor layer, a first electrode in contact with the semiconductor layer, a second electrode separated from the first electrode and in contact with the semiconductor layer, a first insulating layer which covers the first electrode and the second electrode, a gate electrode disposed above the first insulating layer and opposing the semiconductor layer, and the semiconductor layer comprising an aperture located between the first electrode and the second electrode in plan view.