Array Substrate Auxiliary Electrode Via Hole Configuration
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Solution Overview
Problem
In liquid crystal display panels, the large orthogonal projection of the drain on the base substrate due to multiple via holes restricts the pixel aperture ratio, resulting in a small pixel aperture ratio and increased contact resistance between electrodes.
Innovation Solution
The introduction of an auxiliary electrode between the first and second insulating layers, coupled to the drain through a first via hole in the first insulating layer, allows the pixel electrode to connect with the auxiliary electrode through a second via hole in the second insulating layer, reducing the number of via holes and minimizing the orthogonal projection of the drain on the base substrate, thereby increasing the pixel aperture ratio and reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple via holes are used to couple the pixel electrode to the drain, then the electrode connection is achieved, but the orthogonal projection of the drain on the base substrate becomes large
Solution Approach 1:
The patent divides the electrode connection path into multiple segments: the pixel electrode connects to the auxiliary electrode through via holes in the second insulating layer, and the auxiliary electrode connects to the drain through via holes in the first insulating layer. This segmentation allows the via holes to be positioned more compactly, reducing the overall orthogonal projection area of the drain while maintaining reliable electrical connection.
Solution Approach 2:
The auxiliary electrode serves as an intermediary element between the pixel electrode and the drain. By introducing this intermediate connection point, the patent enables a more compact arrangement of via holes and reduces the orthogonal projection area of the drain while ensuring continuous electrical connection through the insulating layers.
2Reliability
If multiple via holes are used to couple the pixel electrode to the drain, then the electrode connection is achieved, but the contact resistance between electrodes increases
Solution Approach 1:
The patent segments the electrode connection into multiple controlled interfaces: pixel electrode to auxiliary electrode through second insulating layer via holes, and auxiliary electrode to drain through first insulating layer via holes. This segmentation allows for optimized via hole positioning and larger via hole areas at each interface, reducing contact resistance while achieving reliable connection.
Solution Approach 2:
The patent applies local quality optimization by positioning via holes with larger cross-sectional areas at critical connection points between electrodes and the auxiliary electrode. The via holes are strategically located to maximize contact area and minimize contact resistance at each interface, while the overall drain projection area is reduced through compact arrangement.
Data Source
AI summary
The disclosure relates to an array substrate. The array substrate may include a base substrate, an auxiliary electrode, a thin film transistor, a first insulating layer, a first electrode, a second insulating layer, and a second electrode sequentially arranged in a direction away from the base substrate. The auxiliary electrode is between the first insulating layer and the second insulating layer and insulated from the first electrode, the auxiliary electrode is coupled to a drain of the thin film transistor through a first via hole in the first insulating layer, and the second electrode is coupled to the auxiliary electrode through a second via hole in the second insulating layer.