Array Substrate Barrier Layer Prevents Copper Diffusion
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Solution Overview
Problem
In large-size, high-resolution TFT-LCDs, the use of metal Cu for source and drain electrodes leads to diffusion into semiconductor and insulating layers, affecting transistor performance and requiring additional patterning processes, which complicates manufacturing and results in unevenness and decreased contrast.
Innovation Solution
An array substrate with a silicon nitride and silicon oxide gate insulating layer and a semiconductor protecting layer, combined with a metal oxide semiconductor barrier layer and transparent conductive materials for forming electrodes, prevents Cu diffusion and simplifies the manufacturing process by using metal Cu for data, source, and drain electrodes, and forming connecting wires through via holes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal Cu is used to form source and drain electrodes, then electrical conductivity is improved, but Cu diffuses into semiconductor and insulating layers affecting transistor performance
Solution Approach 1:
A barrier layer pattern is introduced as an intermediary between the metal Cu electrodes and the semiconductor/insulating layers. This barrier layer prevents Cu diffusion into the underlying layers while allowing the Cu to maintain its electrical conductivity function in the source and drain electrodes.
Solution Approach 2:
The gate insulating layer is divided into two separate layers: a first gate insulating layer and a second gate insulating layer. This segmentation allows the structure to better manage the interface between the Cu electrodes and the semiconductor layer, preventing Cu diffusion while maintaining electrical insulation.
2Object-affected harmful factors
If a barrier layer is deposited before metal Cu to prevent diffusion, then Cu diffusion is prevented, but an additional patterning process is required increasing manufacturing complexity
Solution Approach 1:
The barrier layer pattern formation process is merged with the existing gate electrode patterning process. Both the gate electrode and the barrier layer pattern are formed in the same patterning step, eliminating the need for an additional separate patterning process and reducing manufacturing complexity.
Solution Approach 2:
The barrier layer pattern serves multiple functions: it acts as a diffusion barrier for Cu, defines the source and drain electrode regions, and integrates with the gate electrode structure. This multi-functionality reduces the overall process steps required.
3Ease of manufacture
If wet-etching is used to remove metal Cu, then selective etching is achieved, but the barrier layer remains after etching causing unevenness in subsequent thin film coverage
Solution Approach 1:
The barrier layer pattern is completely removed after the Cu etching process by using a removal layer that selectively dissolves the barrier layer material. This extraction of the barrier layer eliminates the surface unevenness that would otherwise remain after Cu removal, ensuring uniform coverage for subsequent thin film deposition.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Prevents Cu diffusion into the gate insulating and semiconductor layers, improving TFT performance and simplifying the manufacturing process, enabling high mobility and uniformity for large-size liquid crystal displays and OLEDs.
Implementation Method 1
the barrier layer pattern and an active semiconductor layer pattern made of metal oxide semiconductor... to avoid that the amorphous IGZO is damaged when forming the Cu source electrode and drain electrode
Data Source
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AI summary
The present invention provides an array substrate, the method for manufacturing the same, and a liquid crystal display device, wherein the array substrate comprises: a gate electrode, a gate insulating layer, a barrier layer pattern and an active semiconductor layer pattern formed by metal oxide semiconductor which are located on the gate insulating layer, a semiconductor protecting layer which covers the barrier layer pattern and the active semiconductor layer pattern, and has via holes at positions corresponding to the barrier layer pattern and the active semiconductor layer pattern; a data wire, a source electrode and a drain electrode formed by metal Cu, which are located at via holes. Metal Cu is used to form the data wire, the source electrode and the drain electrode, and the metal oxide semiconductor is used as the barrier layer for the metal Cu, and as a result, the diffusion of metal Cu into the layers such as the gate insulating layer etc., is prevented in the manufacturing process of TFT.