Array Substrate Black Matrix Width Optimization for Mura Prevention
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Solution Overview
Problem
Dual gate array substrates face challenges in preventing the Mura phenomenon while maintaining a high aperture ratio, as the difference in widths of the black matrix on data and common electrode lines affects light leakage and display quality.
Innovation Solution
The array substrate design includes a dual gate configuration with data lines and gate lines arranged on either side of sub-pixel column groups, and a black matrix width optimization to minimize the difference ratio between data and common electrode line widths, reducing the likelihood of the Mura phenomenon and enhancing aperture ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the black matrix width on data lines is increased to prevent light leakage, then light leakage is reduced, but the aperture ratio decreases
Solution Approach 1:
The patent applies different black matrix widths to different line types: data lines have a first width while common electrode lines have a second width. This local differentiation allows the data line black matrix to be sufficiently wide to prevent light leakage and Mura phenomenon, while the common electrode line black matrix can be narrower to preserve aperture ratio.
2Area of stationary object
If the black matrix width on common electrode lines is decreased to increase aperture ratio, then aperture ratio is improved, but light leakage control is weakened
Solution Approach 1:
The patent implements asymmetric black matrix design where common electrode lines have a narrower width compared to data lines. This local quality differentiation ensures that aperture ratio is maximized in regions where light leakage control is less critical (common electrode lines), while maintaining adequate light leakage prevention where needed (data lines).
Solution Approach 2:
The patent changes the width parameter of the black matrix based on the functional requirements of different line types. By setting the first width for data lines and a smaller second width for common electrode lines, the design optimizes both light leakage prevention and aperture ratio through parameter differentiation.
3Quantity of substance
If dual gate configuration is implemented to reduce data lines, then the number of data lines is halved, but the complexity of gate line arrangement increases
Solution Approach 1:
The patent divides the gate driving function into two separate gate lines (first gate line and second gate line) for each sub-pixel column group. This segmentation allows each gate line to control specific thin film transistors independently, simplifying the overall control logic while reducing the number of data lines required.
Solution Approach 2:
The dual gate configuration enables each pixel to be controlled through multiple gate lines that can serve universal control functions. The first and second gate lines work together to control the thin film transistors, providing a multi-functional approach to pixel control that reduces data line requirements.
Data Source
Figure 1A~1B
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AI summary
An array substrate and a display panel. The array substrate comprises: multiple sub-pixels (101) arranged along a row direction and a column direction, adjacent four columns of sub-pixel columns or six columns of sub-pixel columns constituting a sub-pixel column group (100); multiple data lines, extending along the column direction, and the data lines comprising a first data line (210) and a second data line (220). Along the row direction, two sides of the sub-pixel column group (100) are respectively provided with the first data line (210) and the second data line (220), and a data line pair (212) consisting of the first data line (210) and the second data line (220) is comprised between adjacent sub-pixel column groups (100).