Array Substrate Bonding Layout for Narrow-Bezel Display Panels
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Solution Overview
Problem
Existing display technologies face challenges in reducing the frame of the display device and increasing the screen-to-body ratio, which affects the overall design and functionality of devices such as smartphones, wearable watches, televisions, and car monitors.
Innovation Solution
The array substrate design includes a first frame area with a chip setting area and bonding areas, featuring driving pads, bonding pins, and peripheral connection lines arranged to optimize the layout, allowing for a more compact design by aligning the chip setting area and bonding areas to minimize the frame width without increasing the overall size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If bonding areas are located on at least one side of the chip setting area in the second direction, then the frame width is reduced and screen-to-body ratio is increased, but the layout complexity of driving pads, bonding pins, and peripheral connection lines increases
Solution Approach 1:
The patent repositions bonding areas from a conventional single-side arrangement to multiple sides of the chip setting area in the second direction. This dimensional redistribution optimizes space utilization, reduces frame width, and improves screen-to-body ratio while managing connection line routing through structured peripheral connection lines.
Solution Approach 2:
The array substrate is divided into distinct functional zones: chip setting area, bonding areas positioned on multiple sides, display area, and frame areas. This segmentation allows independent optimization of each zone, enabling compact integration while maintaining clear separation of functions and reducing overall frame width.
2Ease of manufacture
If peripheral connection lines are arranged to extend to the side of the chip setting area proximate to the bonding area, then component integration is optimized and manufacturing efficiency is improved, but the design complexity of connection line routing increases
Solution Approach 1:
Peripheral connection lines are pre-routed to extend toward the bonding area side of the chip setting area during the design phase. This preliminary arrangement of connection paths facilitates subsequent manufacturing processes, including chip mounting and wire bonding, by establishing predetermined connection routes that simplify assembly operations.
Solution Approach 2:
The peripheral connection lines serve multiple functions: they electrically connect driving pads to bonding pins, provide mechanical support for chip attachment, and define the boundary between active and inactive areas. This multi-functionality reduces the need for separate structural elements, simplifying manufacturing while managing routing complexity.
Data Source
AI summary
An array substrate has a display area and a first frame area which includes a chip setting area and bonding areas. In a second direction, the bonding areas are located on at least one side of the chip setting area. The array substrate includes driving pads in the chip setting area, bonding pins in a bonding area, and peripheral connection lines in the first frame area. An end of each peripheral connection line is connected to a driving pad, and another end thereof is connected to a bonding pin. The peripheral connection lines include first peripheral connection lines extending to a side of the chip setting area proximate to the bonding area in the chip setting area. An end of a first peripheral connection line is connected to a driving pad in the chip setting area, and another end thereof is connected to a bonding pin in the bonding area.