Array Substrate Bonding Terminal Configuration for Chip Compatibility
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing chip bonding process for LCD panels results in poor bonding due to thermal expansion issues, leading to uneven cell gaps and display quality problems, particularly when accommodating different types of chips with varying pin configurations.
Innovation Solution
An array substrate with a bonding area featuring multiple terminal groups and alignment marks allows for selective chip bonding based on chip type, optimizing the bonding process by adjusting the terminal group used for each chip type to reduce the distance between the chip and the substrate edge, thereby improving bonding reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the ACF is cured at a high temperature to bond the chip, then the bonding strength is improved, but the chip and TFT expand causing uneven cell gap and display quality degradation
Solution Approach 1:
The patent segments the terminal groups into different types (first output terminal group with longer terminals, second output terminal group with shorter terminals) to accommodate different chip types. This segmentation allows selective bonding configurations that optimize both bonding strength and cell gap uniformity for each chip type, resolving the contradiction between strong bonding and display quality.
2Adaptability or versatility
If the array substrate accommodates both chip types with different pin configurations, then the versatility is improved, but the chip distance to substrate edge becomes inconsistent leading to poor bonding
Solution Approach 1:
The patent applies local quality by providing different terminal group configurations in different locations on the substrate. The first output terminal group has longer terminals for chips without RAM, while the second output terminal group has shorter terminals for chips with RAM. This localized differentiation allows each chip type to be bonded at an optimal distance from the substrate edge, ensuring both versatility and bonding reliability.
3Adaptability or versatility
If the terminal group length is extended to accommodate smaller chips, then the adaptability is improved, but the distance from chip to substrate edge decreases increasing poor bonding risk
Solution Approach 1:
The patent changes the parameter of terminal group length to create different bonding configurations. By having the first output terminal group with longer terminals and the second output terminal group with shorter terminals, the system can adjust the effective bonding distance parameter based on chip type, maintaining both adaptability to different chip sizes and reliability of bonding.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the likelihood of poor chip bonding and ensures higher display quality by customizing the bonding process for different chip types, enhancing the structural integrity and performance of LCD panels.
Implementation Method 1
using a thermal head to press the chip to electrically connect the chip pins to the bonding terminals on the array substrate through the conductive particles contained in the ACF, and simultaneously converting the ACF from a gel to a solid to bond the chip on the array substrate
Implementation Method 2
when the ACF is cured at a high temperature, the high temperature causes the chip and the thin film transistor (TFT) to also expand
Data Source
AI summary
The invention provides an array substrate and chip bonding method, the array substrate comprising: an active area, and a bonding area located around the active area, wherein the bonding area is provided with an input terminal group, a first output terminal group and a second output terminal a group; the first output terminal group is located at a side of the input terminal group away from the active area, and the second output terminal group is located between the first output terminal group and the input terminal group; when bonding chips, the first output terminal group or the second output terminal group is selected to cooperate with the input terminal group for chip bonding according to the chip type. By simultaneously providing the first and second output terminal groups, the bonding of the second type chip increases the distance between the chip and the edge of the array substrate.