Array Substrate Border Width Reduction via Layer Stacking
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Solution Overview
Problem
The existing design of liquid crystal display panels faces challenges in reducing the width of the border region due to the constraints on the distribution and arrangement of circuit elements and signal lines, making it difficult to achieve a narrower border while ensuring proper operation and manufacturing precision.
Innovation Solution
The array substrate is designed with a laminated structure where the transistor and metal lines are arranged in different layers, allowing their orthographic projections to overlap on the base substrate, thereby reducing the total width occupied in the non-display region and facilitating a narrower border.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the signal lines, transistor electrodes, and common electrode line are arranged in parallel on the same layer in the non-display region, then the manufacturing process is simplified, but the width of the border region increases
Solution Approach 1:
The patent applies dimensionality change by transitioning from a two-dimensional planar arrangement to a three-dimensional stacked arrangement. Specifically, the signal lines are placed in the first metal layer, the transistor electrodes (gate, source, drain) in the second metal layer, and the common electrode line in the third metal layer. This vertical stacking in the third dimension allows the orthographic projections of these components to overlap on the base substrate, thereby reducing the lateral width of the non-display region while maintaining all necessary electrical connections and manufacturing simplicity.
2Length of stationary object
If the width of the non-display region is reduced to achieve a narrower border, then the display device becomes more compact, but the cutting precision requirements during manufacturing increase
Solution Approach 1:
By utilizing the vertical dimension through multi-layer stacking, the patent reduces the lateral footprint of the non-display region without compromising manufacturing precision. The overlapping orthographic projections of components in different layers allow for a narrower border while the layered structure provides natural separation that simplifies the cutting and manufacturing processes, as each layer can be processed and aligned independently.
3Device complexity
If the signal lines and transistor electrodes are placed on the same layer, then the layout is simpler, but the total area occupied in the non-display region increases
Solution Approach 1:
The patent resolves this contradiction by distributing signal lines, transistor electrodes, and common electrode line across three different metal layers (first, second, and third layers respectively). This vertical separation in the third dimension allows their orthographic projections to overlap on the base substrate, significantly reducing the total lateral area occupied in the non-display region while the layered structure itself provides a clear organizational framework that manages layout complexity.
Solution Approach 2:
The patent implements a nested arrangement where the projections of components in different layers overlap and contain one another. The signal lines in the first layer, transistor electrodes in the second layer, and common electrode line in the third layer are positioned such that their projections nest within or overlap each other's projection areas on the base substrate, maximizing space utilization and minimizing the overall non-display region area.
Data Source
AI summary
An array substrate, and a display panel and display device including the same are disclosed. An embodiment of the array substrate comprises a display region and a non-display region. The non-display region comprises: abase substrate; and a first metal layer, a second metal layer, and a third metal layer arranged in a direction perpendicular to the base substrate. A transistor and a metal line are arranged in the non-display region. A gate electrode of the transistor is located in the first metal layer. A source electrode and a drain electrode of the transistor are located in the second metal layer. The metal line is located in the third metal layer. The orthographic projection of the transistor onto the base substrate overlaps, at least partially, with the orthographic projection of the metal line onto the base substrate.