Array Substrate Bottom Gate Polysilicon TFT Uniformity
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Solution Overview
Problem
Existing array substrates for display devices face issues with the stability and mobility of thin film transistors (TFTs) due to thickness differences in active layers, which affect the performance and productivity of both AM-LCD and organic ELD devices, and require additional processing steps and equipment for polycrystalline silicon TFTs.
Innovation Solution
The solution involves forming an array substrate with a bottom gate structure using impurity-doped polycrystalline silicon gate electrodes and intrinsic polycrystalline silicon active layers, where the interlayer insulating layer acts as an etch stopper to maintain uniform thickness and prevent deterioration, eliminating the need for a doping step and reducing fabrication costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a top gate structure with impurity-doped amorphous silicon is used, then the TFT can be formed with conventional processes, but the active layer thickness becomes non-uniform causing deterioration of TFT properties
Solution Approach 1:
The patent inverts the gate structure from top gate to bottom gate configuration. The gate electrode is positioned beneath the active layer instead of above it, which eliminates the thickness variation problem caused by sequential deposition while maintaining compatibility with conventional fabrication processes. This structural inversion resolves the contradiction between ease of manufacture and manufacturing precision.
Solution Approach 2:
The patent changes the material parameter from amorphous silicon to polycrystalline silicon for the active layer. Polycrystalline silicon inherently provides better thickness uniformity and electrical properties compared to amorphous silicon, thus improving manufacturing precision while still allowing conventional processing methods to be used.
2Reliability
If polycrystalline silicon TFTs are fabricated with additional processing steps, then TFT mobility and stability are improved, but fabrication complexity and initial investment increase
Solution Approach 1:
The patent merges the gate electrode and the etch stop layer into a single integrated structure. The gate electrode serves dual functions as both the control element and the protective etch stop layer during subsequent processing steps. This consolidation simplifies the fabrication process by eliminating separate etch stop layer deposition steps while maintaining the improved TFT performance benefits of polycrystalline silicon.
3Illumination intensity
If the aperture ratio is increased to improve display brightness, then the storage capacitor capacitance decreases affecting image quality
Solution Approach 1:
The patent utilizes the vertical dimension by forming the storage capacitor in the thickness direction rather than solely in the planar area. The bottom gate structure allows the storage capacitor to be formed using the vertical space between the substrate and the active layer, enabling capacitance enhancement without consuming additional lateral area that would reduce the aperture ratio.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the mobility and stability of TFTs, prevents deterioration due to thickness differences, and increases the capacitance of storage capacitors without reducing the aperture ratio, while simplifying the fabrication process and reducing initial investment for additional equipment.
Implementation Method 1
the interlayer insulating layer acts as an etch stopper to maintain uniform thickness and prevent deterioration
Implementation Method 2
impurity-doped polycrystalline silicon gate electrodes
Implementation Method 3
intrinsic polycrystalline silicon active layers
Data Source
AI summary
An array substrate for a display device includes: a substrate; first and second gate electrodes of impurity-doped polycrystalline silicon on the substrate; a gate insulating layer on the first and second gate electrodes; first and second active layers of intrinsic polycrystalline silicon on the gate insulating layer, the first and second active layers corresponding to the first and second active layers, respectively; an interlayer insulating layer on the first and second active layers and including first to fourth active contact holes, the first and second active contact holes exposing side portions of the first active layer, the third and fourth active contact holes exposing side portions of the second active layer; first and second ohmic contact layers of impurity-doped amorphous silicon on the interlayer insulating layer, the first ohmic contact layer contacting the first active layer through the first and second active contact holes, the second ohmic contact layer contacting the second active layer through the third and fourth active contact hole; first source and drain electrodes on the first ohmic contact layer and second source and drain electrodes on the second ohmic contact layer; a data line on the interlayer insulating layer, the data line connected to the first source electrode; a first passivation layer on the first source and drain electrodes, the second source and drain electrodes and the data line; a gate line on the first passivation layer, the gate line connected to the first gate electrode and crossing the data line to define a pixel region; a second passivation layer on the gate line; and a pixel electrode on the second passivation layer, the pixel electrode connected to the second drain electrode.