Array Substrate Bridge Electrode Layout for Deep-Hole Connectivity

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Solution Overview

Problem

The 5mask architecture in FFS and IPS liquid crystal display panels faces challenges in forming deep holes due to the use of different etching methods for transparent conductive materials and inorganic materials, leading to poor connection between the pixel electrode and common electrode, which affects the manufacturing success rate and connectivity.

Innovation Solution

The array substrate design includes a pixel electrode layer with a bridge electrode that forms through holes in the common electrode, first passivation layer, and gate insulation layer, allowing for simultaneous etching without obstruction by the common electrode, thereby improving the connection between the common electrode and common electrode line.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the 5mask architecture is used with the common electrode layer positioned in the middle, then the distance between electrodes is reduced improving liquid crystal rotation and lowering operating voltage, but the pixel thickness increases to 13000 A making deep hole formation difficult

Engineering Contradiction:
Improveconnection reliabilityVSAvoiddeep hole formation difficulty
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The common electrode layer is segmented into two parts: a first common electrode layer positioned closer to the pixel electrode for forming the electric field, and a second common electrode layer positioned farther away for providing a reference potential. This segmentation allows the pixel electrode to connect to the first common electrode layer through a shorter distance, making deep hole formation easier while maintaining the electrical connection function

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a vertical dimension differentiation by positioning the two common electrode layers at different depths within the substrate. The first common electrode layer is placed at a shallower depth to facilitate connection with the pixel electrode, while the second common electrode layer is placed at a deeper depth to maintain the overall electrode configuration. This dimensional arrangement solves the deep hole formation problem by creating a staged electrode structure

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Manufacturing precision

If different etching methods are used for transparent conductive materials and inorganic materials, then material-specific etching precision is achieved, but the manufacturing process complexity increases and connection reliability decreases

Engineering Contradiction:
Improveetching precisionVSAvoidetching process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies the same etching method to both the first passivation layer and the gate insulation layer when forming the connection hole. This homogeneous etching approach simplifies the manufacturing process by eliminating the need to switch between different etching methods, while still achieving adequate precision for connecting the pixel electrode to the common electrode line

Inventive Principle:
Principle #33Homogeneity

Solution Approach 2:

The connection hole structure serves multiple functions: it connects the pixel electrode to the common electrode line, provides a pathway for electrical connection, and accommodates the bridge electrode. The single etching process used to form this hole achieves all these functions simultaneously, reducing process complexity while maintaining manufacturing precision

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12436432B2Array substrate and liquid crystal display panel
Publication Date: 2025.10.07 GUANGZHOU CHINA STAR OPTOELECTRONICS SEMICON DISPLAY TECH CO LTD
  • US12436432B2 patent drawing
  • US12436432B2 patent drawing
  • US12436432B2 patent drawing

AI summary

An array substrate includes a substrate, a common electrode line, a gate insulation layer, a common electrode, a first passivation layer, and a pixel electrode layer that are stacked in sequence. The pixel electrode layer includes a pixel electrode and a bridge electrode insulated from the pixel electrode. A first through hole is opened in the common electrode, a second through hole is opened in the first passivation layer, a third through hole is opened in the gate insulation layer, the third through hole exposes the common electrode line, an orthographic projection of a hole wall of the first through hole on the substrate is a first orthographic projection, an orthographic projection of a hole wall of the second through hole on the substrate is a second orthographic projection, and the first orthographic projection partially overlaps the second orthographic projection.