Array Substrate Bridging Structure for TFT Circuit Fracture Prevention
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Solution Overview
Problem
The array substrate in TFT-LCD devices often experiences fractures in local circuit structures due to unreasonable partial design, leading to abnormal circuit functioning and reduced yield.
Innovation Solution
The array substrate design includes a carrier substrate with a display and non-display area, featuring a first signal line, insulating layers with through holes and connecting grooves, and a bridging layer that connects signal lines through these holes, utilizing multiple insulating layers with different materials to reduce etching depth and improve through hole morphology, thereby minimizing bridging layer breakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a single insulating layer is used to cover signal lines, then the manufacturing process is simpler, but the etching depth is excessive and through hole morphology is poor, leading to bridging layer breakage
Solution Approach 1:
The patent divides the single insulating layer into multiple sub-layers (first insulating layer, second insulating layer, third insulating layer) with different materials and properties. This segmentation allows each layer to be etched to appropriate depths, creating well-formed through holes that connect properly without causing bridging layer breakage, thus resolving the contradiction between manufacturing precision and device complexity.
Solution Approach 2:
Different insulating layers are made from different materials (e.g., silicon oxide, silicon nitride, organic insulating layers) with different etching characteristics. This local quality differentiation enables selective etching to achieve optimal through hole morphology at each level, preventing bridging layer breakage while maintaining reasonable structural complexity.
2Reliability
If the insulating layer is made thinner to reduce etching depth, then bridging layer breakage risk decreases, but electrical insulation performance deteriorates
Solution Approach 1:
The patent uses composite insulating layer structures with multiple materials (silicon oxide, silicon nitride, organic insulating materials) stacked in specific configurations. This composite approach provides both adequate electrical insulation performance and controlled etching depth, ensuring bridging layer integrity while maintaining proper insulation thickness where needed.
3Productivity
If circuit structure density is increased to improve integration, then device functionality improves, but the risk of circuit fractures and manufacturing defects increases
Solution Approach 1:
The patent introduces vertical dimensionality through multiple insulating layers and strategically positioned through holes to connect signal lines across different levels. This three-dimensional arrangement allows higher circuit integration density while maintaining reliability by providing multiple connection paths and reducing stress on individual circuit elements.
Data Source
AI summary
The array substrate includes a carrier substrate, a first signal line, a first insulating layer, a second signal line, a thin film transistor, a second insulating layer, and a bridging layer. The first insulating layer covers the first signal line and provides with a first through hole exposing the first signal line; the second signal line is located on a side of the first insulating layer; the second insulating layer covers the thin film transistor and the second signal line, and provides with a second through hole, a third through hole, and a connecting groove, and the connecting groove is in communication with the second through hole and the third through hole; the bridging layer is located in the connecting groove, connected to the first signal line through the second through hole and the first through hole, and connected to the second signal line through the third through hole.