Array Substrate Conductive Overlap Tuning for Uniform AMOLED Brightness
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Solution Overview
Problem
Existing AMOLED display panels face issues with inconsistent compensation durations in pixel driving circuits, leading to differences in brightness between odd and even numbered rows, affecting display quality due to varying parasitic capacitances in conductive connections.
Innovation Solution
The array substrate design includes alternately arranged odd and even numbered row circuit groups with conductive patterns in different layers, reducing overlapping areas and parasitic capacitances to equalize compensation durations, ensuring consistent brightness across rows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conductive patterns are placed in multiple layers with overlapping projections, then device complexity is reduced and manufacturing is simplified, but parasitic capacitance increases causing brightness inconsistency between odd and even rows
Solution Approach 1:
The patent applies asymmetry by intentionally creating different overlapping areas between conductive patterns in odd-numbered and even-numbered row circuit groups. Specifically, the overlapping area in odd-numbered rows is designed to be smaller than in even-numbered rows, which asymmetrically adjusts the parasitic capacitance values to achieve consistent compensation durations across all rows.
Solution Approach 2:
The patent implements local quality by varying the overlapping area of conductive patterns at different locations (odd vs even rows) to achieve uniform electrical characteristics. The conductive patterns are locally adjusted in their overlapping dimensions to compensate for position-dependent parasitic capacitance variations, ensuring consistent display performance across the entire panel.
2Manufacturing precision
If conductive connection patterns use continuous designs for simplicity, then manufacturing precision is improved, but parasitic capacitance varies between odd and even rows causing compensation duration inconsistency
Solution Approach 1:
The patent uses asymmetry to differentiate the overlapping areas of conductive connection patterns between odd and even rows. While maintaining continuous pattern designs for manufacturing simplicity, the overlapping dimensions are asymmetrically adjusted so that odd-numbered rows have smaller overlapping areas than even-numbered rows, thereby equalizing the compensation durations despite the continuous pattern structure.
3Duration of action of moving object
If parasitic capacitance is reduced by minimizing overlapping areas, then compensation duration consistency is improved, but device complexity increases due to different pattern designs for odd and even rows
Solution Approach 1:
The patent applies local quality by implementing position-specific overlapping area adjustments in the conductive patterns. Odd-numbered row circuit groups have smaller overlapping areas while even-numbered rows have larger overlapping areas, creating local variations that compensate for parasitic capacitance differences and achieve uniform compensation durations across the entire display panel.
Data Source
AI summary
An array substrate includes a substrate, pixel driving circuits and conductive patterns. In each pixel driving circuit, a first electrode region of a driving transistor, a second electrode region of a data writing transistor and a second electrode region of a first light-emitting control transistor are connected through a conductive connection pattern. The pixel driving circuits are configured as odd-numbered row circuit groups and even-numbered row circuit groups. The odd-numbered row circuit groups and the even-numbered row circuit groups each include pixel driving circuits. An overlapping area of orthographic projections, of the substrate, of a conductive connection pattern and a conductive pattern in at least one pixel driving circuit in an odd-numbered row circuit group is less than an overlapping area of orthographic projections, on the substrate, of a conductive connection pattern and a conductive pattern in at least one pixel driving circuit in an even-numbered row circuit group.