Array Substrate Conductive Buffer Layer Oxidation Prevention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The use of low-resistance metals like copper in display devices leads to surface oxidation during the etching process, resulting in poor conductive performance due to the formation of oxidized connections.
Innovation Solution
A method for manufacturing an array substrate that includes forming a conductive buffer layer between the pixel electrode and gate metal layers, using a grayscale mask to selectively etch the layers, and electrically connecting the source/drain metal layer with the pixel electrode layer through a via hole, thereby avoiding direct connection with the oxidized gate metal layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If low-resistance metals like copper are used in conductive members, then electrical resistance is reduced, but surface oxidation occurs during etching process resulting in poor conductive performance
Solution Approach 1:
A conductive buffer layer is introduced between the pixel electrode layer and the gate metal layer. This buffer layer acts as an intermediary that prevents direct contact between the low-resistance metal (copper) and the etching environment, thereby preventing surface oxidation while maintaining electrical conductivity. The buffer layer is selectively removed in grayscale exposed areas to establish electrical connections where needed.
2Manufacturing precision
If traditional multi-mask processes are used to form connection patterns, then precise electrical connections can be achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent combines multiple mask processes into a single grayscale mask process. By using a grayscale mask plate with different light transmission rates, the method simultaneously forms multiple connection patterns (fully exposed areas, grayscale exposed areas, and unexposed areas) in one step, reducing the number of masks from multiple to one while maintaining precise electrical connections.
Solution Approach 2:
The invention utilizes grayscale exposure parameters to create different exposure levels (fully exposed, grayscale exposed, unexposed areas) in a single mask process. By controlling the light transmission rate of the mask plate and exposure conditions, precise connection patterns are formed without requiring multiple sequential mask steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents surface oxidation of low-resistance metals, ensuring stable conductive performance and reducing the number of mask processes required, thus enhancing manufacturing efficiency and cost-effectiveness.
Implementation Method 1
forming a photoresist layer on the gate metal layer, forming a fully exposed area, an unexposed area and a grayscale exposed area in the photoresist layer using a grayscale mask plate through an exposure-and-development process
Data Source
AI summary
The embodiments of present disclosure disclose an array substrate, a method for manufacturing the array substrate, and a display device. The method includes forming a pixel electrode layer, a gate metal layer, and a source/drain metal layer on a base substrate, the pixel electrode layer including a first connection part pattern, the gate metal layer including a second connection part pattern, the source/drain metal layer including a third connection part pattern, wherein the first connection part pattern and the second connection part pattern overlap, and a portion of the first connection part pattern extending beyond the second connection part pattern is electrically connected with the third connection part pattern through a first via hole.