Array Substrate Buffer Layer Through-Holes for Short-Circuit Prevention

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Solution Overview

Problem

In existing array substrate fabrication, foreign substances can penetrate the buffer layer and cause short-circuiting between gate lines and data lines, degrading the active layer performance and hindering proper image display.

Innovation Solution

Incorporating a buffer layer with through-holes at the intersection areas of gate and data lines, and an interlayer dielectric layer with grooves, to prevent foreign substances from reaching the insulation layer and ensuring proper alignment and formation of gate and data lines, along with filling sections to maintain structural integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a buffer layer is arranged between the active layer and the underlying substrate to prevent components from entering the active layer, then the active layer performance is protected, but foreign substances can penetrate the buffer layer and cause short-circuiting between gate lines and data lines

Engineering Contradiction:
Improveactive layer performanceVSAvoidforeign substance penetration
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The buffer layer is segmented by forming through-holes at the intersection areas of gate lines and data lines. This segmentation allows the buffer layer to selectively block foreign substances in critical areas while maintaining structural integrity and electrical isolation where needed.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Through-holes are extracted from the buffer layer at intersection areas to remove the blocking function in specific locations. This allows proper formation of gate and data lines at intersections while the buffer layer continues to protect other areas from foreign substance penetration.

Inventive Principle:
Principle #2Taking out (Extraction)

2Object-affected harmful factors

If through-holes are formed in the buffer layer at intersection areas to prevent short-circuiting, then foreign substance penetration is blocked, but the structural integrity of the buffer layer is compromised

Engineering Contradiction:
Improveshort-circuit preventionVSAvoidbuffer layer integrity
Core Design Contradiction:
Object-affected harmful factorsVSStability of the object's composition

Solution Approach 1:

The buffer layer is given different properties in different locations: intact in areas requiring foreign substance blocking, and perforated with through-holes at intersection areas where line formation is required. This local differentiation maintains overall buffer layer functionality while enabling necessary electrical connections.

Inventive Principle:
Principle #3Local quality

3Reliability

If gate lines and data lines are formed on the buffer layer without through-holes, then the buffer layer maintains its protective function, but foreign substances can cause short-circuiting between intersecting lines

Engineering Contradiction:
Improveelectrical isolationVSAvoidforeign substance induced short-circuit
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

Through-holes act as intermediary structures that mediate between the buffer layer's protective function and the need for electrical connections at line intersections. The through-holes allow gate and data lines to be formed without foreign substance interference while the surrounding buffer layer material continues to provide protection.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11527599B2Array substrate, method for fabricating the same display panel, and display device
Publication Date: 2022.12.13 HEFEI XINSHENG OPTOELECTRONICS TECH CO LTD
  • US11527599B2 patent drawing
  • US11527599B2 patent drawing
  • US11527599B2 patent drawing

AI summary

Disclosed are an array substrate, a method for fabricating the same, a display panel, and a display device, and the array substrate includes: an underlying substrate, and gate lines and data lines located on the underlying substrate, and intersecting with each other, a layer where the gate lines are located is between a layer where the data lines are located, and the underlying substrate; and the array substrate further includes a buffer layer located between the underlying substrate and the layer where the gate lines are located; and the buffer layer includes a plurality of through-holes, where orthographical projections of the through-holes onto the underlying substrate cover orthographical projections of the areas where the gate lines intersect with the data lines, onto the underlying substrate.