Array Substrate Charge Sharing Capacitor Aperture Ratio

The patent utilizes the vertical stacking dimension to form the charge sharing capacitor. The first metal layer (scan line or charge sharing line) and second metal layer (source or drain electrode) are stacked vertically with an insulating layer between them, creating a three-dimensional capacitor structure. This vertical arrangement allows the capacitor to occupy non-display area in the planar view, preventing occupation of the display region and thereby maintaining high pixel aperture ratio while still forming a functional charge sharing capacitor.

The patent extracts the charge sharing capacitor structure from the display region and relocates it to the non-display region. By positioning the first and second metal layers of the capacitor in the non-display area (with the trace region serving as the location), the capacitor function is preserved while the display region area is maximized. This extraction principle separates the capacitor formation from the active display area, resolving the area conflict.

The patent introduces an insulating layer as an intermediary between the first metal layer (charge sharing line) and the second metal layer (source or drain electrode). This insulating layer serves dual purposes: it provides electrical insulation to prevent short circuits while allowing the two metal layers to be in close proximity for effective capacitive coupling. The insulating layer acts as a mediator that enables both the electrical connection for capacitor function and the spatial arrangement for high aperture ratio.