Array Substrate Extended Storage Capacitor for LCD Uniformity
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Solution Overview
Problem
In liquid crystal display (LCD) panels, especially those with a dual-gate line structure, uneven parasitic capacitance between signal lines leads to luminance irregularities, resulting in vertical stripes of alternate columns.
Innovation Solution
The introduction of an extended storage capacitor connected in parallel to the existing storage capacitor in each sub-pixel, increasing the overall capacitance and improving display uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the capacitance of the storage capacitor is increased to compensate for coupling capacitances, then display uniformity is improved, but the device structure becomes more complex
Solution Approach 1:
The storage capacitor is divided into two separate capacitors (first storage capacitor and second storage capacitor) connected in parallel. Each capacitor has its own first electrode and second electrode, allowing the total capacitance to be increased while distributing the structural complexity across multiple simpler units rather than one complex capacitor
Solution Approach 2:
The first storage capacitor and second storage capacitor are connected in parallel to combine their capacitance values. This merging of parallel capacitors achieves the desired total capacitance increase to compensate for coupling capacitance effects while using standard capacitor design patterns
2Reliability
If the area of the storage capacitor is increased to increase capacitance, then coupling capacitance impact is reduced, but the sub-pixel area available for other components decreases
Solution Approach 1:
The capacitors are arranged in a layered vertical structure where first electrodes and second electrodes are positioned at different heights (different Z-dimensions) within the sub-pixel. This three-dimensional arrangement increases capacitance by utilizing vertical space rather than horizontal area, preserving more sub-pixel area for other components like liquid crystal material and color filters
Solution Approach 2:
The capacitor structures are nested within the sub-pixel volume by positioning electrodes at different vertical levels. The first electrodes and second electrodes are arranged such that they occupy different spatial zones, effectively nesting the capacitor functionality within the existing sub-pixel footprint without requiring additional lateral area
3Manufacturing precision
If the distance between signal lines is reduced to increase resolution, then display resolution is improved, but coupling capacitance between lines increases
Solution Approach 1:
The increased storage capacitance (0.20-0.35 pF) is designed in advance to counteract and compensate for the coupling capacitance effects that arise from closely spaced signal lines. This preliminary anti-action approach proactively offsets the harmful coupling effects before they can significantly impact display performance, enabling tighter signal line spacing
4Reliability
If the capacitance value is increased to maintain voltage during screen holding phase, then display uniformity is improved, but more manufacturing layers are required
Solution Approach 1:
The gate electrode layer and source-drain electrode layer serve dual functions: they act as functional circuit elements (gate and source/drain connections) and simultaneously serve as the second electrodes for both the first and second storage capacitors. This multi-functionality increases capacitance while minimizing additional manufacturing layers by reusing existing structural layers
Data Source
AI summary
Provided is an array substrate. The array substrate includes a plurality of sub-pixels; wherein a storage capacitor and an extended storage capacitor are disposed in each of the plurality of sub-pixels, the extended storage capacitor and the storage capacitor being connected in parallel; and the array substrate includes a gate electrode layer, a source and drain electrode layer, and a pixel electrode.