Array Substrate Layout for TFT Channel Width Control
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Solution Overview
Problem
Traditional array substrates fail to meet the requirements of switching characteristics and clarity due to excessive width differences between the channel region and the gate, caused by diffusion phenomena, leading to potential loss of switching characteristics in thin film transistors.
Innovation Solution
The array substrate design includes a base substrate with a buffer layer, active layer, gate insulation layer, and first gate, where the active layer has two second active layers on either side, forming a channel region, and an interlayer insulation layer with through holes for source and drain connections, ensuring the width difference between the channel region and the gate is within a preset range, using the first gate as a conductive mask to prevent plasma bombardment and maintain channel region length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Illumination intensity
If the gate width is reduced to meet display panel clarity requirements, then the display clarity is improved, but the channel region width becomes excessively smaller than the gate width due to diffusion, causing loss of switching characteristics
Solution Approach 1:
The patent introduces a third dimension by adding overlapping active layers above and below the channel-forming active layer. This vertical stacking allows the channel region width to extend beyond the gate width in the vertical direction, compensating for the horizontal width reduction caused by diffusion. The channel width in the vertical dimension (through the overlapping layers) makes up for the reduced horizontal width, maintaining adequate channel dimensions for proper switching characteristics while keeping the gate width small for display clarity.
Solution Approach 2:
The patent embeds the channel-forming active layer between two overlapping active layers, creating a nested structure. The gate is positioned to overlap with the channel-forming active layer, while the overlapping active layers extend beyond the gate boundaries. This nesting arrangement allows the channel region to effectively occupy a larger three-dimensional volume than the gate footprint, ensuring sufficient channel width for switching operation even when the gate width is reduced for clarity requirements.
2Reliability
If the channel region width is kept close to gate width to maintain switching characteristics, then the switching characteristics are improved, but the manufacturing precision becomes difficult to ensure due to diffusion effects
Solution Approach 1:
The patent moves the channel width control problem from a two-dimensional planar constraint to a three-dimensional solution. By stacking overlapping active layers vertically, the effective channel width is determined by both horizontal and vertical dimensions. This dimensional transition provides design flexibility to compensate for manufacturing variations and diffusion effects, making it easier to achieve consistent switching characteristics despite variations in lateral alignment and diffusion extent.
Solution Approach 2:
The patent changes the geometric parameters of the active layer structure by introducing vertical overlap. Instead of relying solely on precise lateral dimension control, the design uses vertical extension of overlapping layers to ensure adequate channel width. This parameter change from purely lateral dimensions to combined lateral and vertical dimensions provides a more robust solution that is less sensitive to manufacturing precision variations in the lateral direction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces the width difference caused by diffusion, ensuring the switching characteristics and clarity requirements of thin film transistors are met, preventing short-channel effects and maintaining the size requirements of display panels.
Implementation Method 1
using the first gate as a conductive mask to prevent plasma bombardment and maintain channel region length
Implementation Method 2
due to the diffusion phenomenon in different conductive processes, an actual width of the channel region is smaller than a width of the gate
Data Source
AI summary
The present application relates to the technical field of display panels, and provides an array substrate and a method for preparing the same, and a display panel. The array substrate includes a base substrate, a buffer layer, an active layer, a gate insulation layer, a first gate, an interlayer insulation layer, a source and a drain that are laminated. The active layer includes the first active layer and the two second active layers, and the first active layer forms the channel region.